參數(shù)資料
型號(hào)： Embedded Pentium 133
廠商： Intel Corp.
英文描述： 32 BIT Embedded Pentium Processor(32位嵌入式奔騰處理器)
中文描述： 32位嵌入式奔騰處理器（32位嵌入式奔騰處理器）
文件頁(yè)數(shù)： 16/42頁(yè)
文件大?。?/td> 882K
代理商： EMBEDDED PENTIUM 133
Embedded Pentium
Processor
16
Datasheet
Table 4. Pin Quick Reference (Sheet 1 of 5)
Symbol
Type
Name and Function
A20M#
I
When the
address bit 20 mask
pin is asserted, the processor emulates the address
wraparound at 1 Mbyte that occurs on the 8086 by masking physical address bit 20
(A20) before performing a lookup to the internal caches or driving a memory cycle
on the bus. The effect of A20M# is undefined in protected mode. A20M# must be
asserted only when the processor is in real mode.
A20M# is internally masked by the processor when configured as a Dual processor.
A31–A3
I/O
As outputs, the
address
lines
of the processor along with the byte enables define
the physical area of memory or I/O accessed. The external system drives the inquire
address to the processor on A31–A5.
ADS#
O
The
address strobe
indicates that a new valid bus cycle is currently being driven by
the processor.
ADSC#
O
The
additional address strobe
signal is functionally identical to ADS#. This signal
can be used to relieve tight board timings by easing the load on the ADS# signal.
AHOLD
I
In response to the assertion of
address hold
, the processor stops driving the
address lines (A31–A3), and AP in the next clock. The rest of the bus remains active
so data can be returned or driven for previously issued bus cycles.
AP
I/O
Address parity
is driven by the processor with even parity information on all
processor generated cycles in the same clock in which the address is driven. Even
parity must be driven back to the processor during inquire cycles on this pin in the
same clock as EADS# to ensure that the correct parity check status is indicated by
the processor.
APCHK#
O
The
address parity check
status pin is asserted two clocks after EADS# is sampled
active if the processor has detected a parity error on the address bus during inquire
cycles. APCHK# remains active for one clock each time a parity error is detected
(including during dual processing private snooping).
[APICEN]
PICD1
I
Advanced programmable interrupt controller enable
enables or disables the on–
chip APIC interrupt controller. If sampled high at the falling edge of RESET, the APIC
is enabled. APICEN shares a pin with the PICD1 signal.
BE7#–BE5#
BE4#–BE0#
O
I/O
The
byte enable
pins determine which bytes must be written to external memory, or
which bytes were requested by the CPU for the current cycle. The byte enables are
driven in the same clock as the address lines (A31–A3).
The lower four byte enable pins (BE3#–BE0#) are used as APIC ID inputs and are
sampled at RESET.
In dual processing mode, BE4# is used as an input during Flush cycles.
BF1–BF0
I
Bus frequency
determines the bus-to-core frequency ratio. BF1–BF0 are sampled
at RESET, and cannot be changed until another non-warm (1 ms) assertion of
RESET. Additionally, BF1–BF0 must not change values while RESET is active. See
Table 5 for bus frequency selections.
BOFF#
I
The
backoff
input is used to abort all outstanding bus cycles that have not yet
completed. In response to BOFF#, the processor floats all pins normally floated
during bus hold in the next clock. The processor remains in bus hold until BOFF# is
negated, at which time the processor restarts the aborted bus cycle(s) in their
entirety.
BP3–BP2
PM1/BP1–
PM0/BP0
O
The
breakpoint
pins (BP3–BP0) correspond to the debug registers, DR3–DR0.
These pins externally indicate a breakpoint match when the debug registers are
programmed to test for breakpoint matches.
BP1 and BP0 are multiplexed with the
performance monitoring
pins (PM1 and
PM0). The PB1 and PB0 bits in the Debug Mode Control Register determine if the
pins are configured as breakpoint or performance monitoring pins. The pins come
out of RESET configured for performance monitoring.
The pins are classified as Input or Output based on their function in Master Mode. See the Pentium
Processor
Family Developer’s Manual
(order number 273204) for more information.
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