參數(shù)資料
型號(hào)： Embedded Pentium 133
廠商： Intel Corp.
英文描述： 32 BIT Embedded Pentium Processor(32位嵌入式奔騰處理器)
中文描述： 32位嵌入式奔騰處理器（32位嵌入式奔騰處理器）
文件頁(yè)數(shù)： 20/42頁(yè)
文件大?。?/td> 882K
代理商： EMBEDDED PENTIUM 133
Embedded Pentium
Processor
20
Datasheet
PHIT#
I/O
Private inquire cycle hit/miss
is a hit indication used to maintain local cache
coherency when two Pentium processors are configured in dual processing mode.
PHIT# should be left unconnected if only one Pentium processor exists in a system.
PHITM#
I/O
Private inquire cycle hit/miss to a modified line
is a hit indication used to
maintain local cache coherency when two Pentium processors are configured in
dual processing mode. PHITM# should be left unconnected if only one Pentium
processor exists in a system.
PICCLK
I
The APIC interrupt controller serial data bus clock is driven into the
processor
interrupt controller clock
input of the processor.
PICD1/[DPEN#]–
PICD0/[APICEN]
I/O
Processor interrupt controller data lines 0
–
1
of the processor comprise the data
portion of the APIC 3-wire bus. They are open-drain outputs that require external
pull-up resistors. These signals share pins with DPEN# and APICEN respectively.
PM1/BP1–
PM0/BP0
O
These pins function as part of the performance monitoring feature.
The breakpoint 1–0 pins are multiplexed with the
performance monitoring 1
–
0
pins. The PB1 and PB0 bits in the Debug Mode Control Register determine whether
the pins are configured as breakpoint or performance monitoring pins. The pins
come out of RESET configured for performance monitoring.
PRDY
O
The
probe ready
output pin indicates that the processor has stopped normal
execution in response to the R/S# pin going active, or Probe Mode being entered.
SMIACT#
O
An active
system management interrupt active
output indicates that the processor
is operating in System Management Mode.
STPCLK#
I
Assertion of the
stop clock
input signifies a request to stop the internal clock of the
processor, which causes the core to consume less power. When the processor
recognizes STPCLK#, the processor stops execution on the next instruction
boundary, unless superseded by a higher priority interrupt, and generates a stop
grant acknowledge cycle. When STPCLK# is asserted, the processor still responds
to interprocessor and external snoop requests.
TCK
I
The
testability clock input
provides the clocking function for the Pentium processor
boundary scan in accordance with the IEEE Boundary Scan interface (Standard
1149.1). It is used to clock state information and data into and out of the processor
during boundary scan.
TDI
I
The
test data input
is a serial input for the test logic. TAP instructions and data are
shifted into the processor on the TDI pin on the rising edge of TCK when the TAP
controller is in an appropriate state.
TDO
O
The
test data output
is a serial output of the test logic. TAP instructions and data
are shifted out of the processor on the TDO pin on TCK’s falling edge when the TAP
controller is in an appropriate state.
TMS
I
The value of the
test mode select
input signal sampled at the rising edge of TCK
controls the sequence of TAP controller state changes.
TRST#
I
When asserted, the
test reset
input allows the TAP controller to be asynchronously
initialized.
V
CC
V
SS
I
The Pentium processor has 53 3.3 V
power
inputs.
I
The Pentium processor has 53
ground
inputs.
W/R#
O
Write/read
is one of the primary bus cycle definition pins. It is driven valid in the
same clock in which the ADS# signal is asserted. W/R# distinguishes between write
and read cycles.
WB/WT#
I
The
write back/write through
input allows a data cache line to be defined as write
back or write through on a line-by-line basis. As a result, it determines whether a
cache line is initially in the S or E state in the data cache.
The pins are classified as Input or Output based on their function in Master Mode. See the Pentium
Processor
Family Developer’s Manual
(order number 273204) for more information.
Table 4. Pin Quick Reference (Sheet 5 of 5)
Symbol
Type
Name and Function
相關(guān)PDF資料
PDF描述
Embedded Pentium 166 32 Bit Embedded Pentium Processor(32位嵌入式奔騰處理器)
Embedded Pentium 233 32 BIT Embedded Pentium Processor with MMX Technology(32位嵌入式帶MMX技術(shù)奔騰處理器)
Embedded Pentium 200 32 Bit Embedded Pentium Processor with MMX Technology(32位嵌入式帶MMX技術(shù)奔騰處理器)
Embedded Pentium 266 Low-Power Embedded Pentium Processor with MMX Technology(低能量嵌入式帶MMX技術(shù)奔騰處理器)
EMBMOD133 Intel Embedded Processor Module(英特爾嵌入式微處理器模塊)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EMBER ZIGBEE DEV KIT W/PCWH 制造商:Custom Computer Services (CCS) 功能描述:KIT DEV EMBER ZIGBEE W/PCWH
EMB-ET850-22 制造商:IBase Technology (USA) Inc. 功能描述:ET850 COM-E AMD N54L (2.2G) V/L - Bulk
EM-BFG11905-NJ 功能描述:900MHZ FIBERGLASS BASESTATION AN 制造商:nearson inc. 系列:- 包裝:散裝 零件狀態(tài):在售 頻率組:UHF（300 MHz ~ 1 GHz） 頻率（中心/帶）:915MHz 頻率范圍:902MHz ~ 928MHz 天線類型:鞭狀，直形 頻帶數(shù):1 VSWR:1.5 回波損耗:- 增益:5dBi 功率 - 最大值:100W 特性:- 端接:連接器，N 母型 侵入防護(hù):IP66 安裝類型:連接器安裝 高度（最大值）:20.669"（525.00mm） 應(yīng)用:- 標(biāo)準(zhǔn)包裝:1
EMB-FTP-T-TM4C129-21P 制造商:InterNiche Technologies 功能描述:EMBFTP (SERVER) - Virtual or Non-Physical Inventory (Software & Literature)
EMBFTP-T-TM4C129-21P 制造商:InterNiche Technologies 功能描述:EMBTCP - Virtual or Non-Physical Inventory (Software & Literature)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*