參數(shù)資料
型號: ENC424J600-I/PT
廠商: Microchip Technology
文件頁數(shù): 101/168頁
文件大?。?/td> 0K
描述: IC ETHERNET CTRLR W/SPI 44-TQFP
視頻文件: Fast 100 Mbps Ethernet PICtail Plus Overview
標準包裝: 160
控制器類型: 以太網(wǎng)控制器(IEEE 802.3)
接口: SPI
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 96mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應(yīng)商設(shè)備封裝: 44-TQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 684 (CN2011-ZH PDF)
配用: AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
PIC16CR7X
DS21993C-page 36
2007 Microchip Technology Inc.
4.4
PORTD and TRISD Registers
This section is not applicable to the PIC16CR73 or
PIC16CR76.
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configureable as an input or
output.
PORTD can be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL.
FIGURE 4-6:
PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
TABLE 4-7:
PORTD FUNCTIONS
TABLE 4-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Data Bus
WR Port
WR TRIS
RD Port
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Input
Buffer
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
Q
D
CK
Q
D
CK
EN
QD
EN
Name
Bit#
Buffer Type
Function
RD0/PSP0
bit 0
ST/TTL(1)
Input/output port pin or parallel slave port bit 0
RD1/PSP1
bit 1
ST/TTL(1)
Input/output port pin or parallel slave port bit 1
RD2/PSP2
bit 2
ST/TTL(1)
Input/output port pin or parallel slave port bit 2
RD3/PSP3
bit 3
ST/TTL(1)
Input/output port pin or parallel slave port bit 3
RD4/PSP4
bit 4
ST/TTL(1)
Input/output port pin or parallel slave port bit 4
RD5/PSP5
bit 5
ST/TTL(1)
Input/output port pin or parallel slave port bit 5
RD6/PSP6
bit 6
ST/TTL(1)
Input/output port pin or parallel slave port bit 6
RD7/PSP7
bit 7
ST/TTL(1)
Input/output port pin or parallel slave port bit
Legend:
ST = Schmitt Trigger input, TTL = TTL input
Note 1:
Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
08h
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
88h
TRISD
PORTD Data Direction Register
1111 1111
89h
TRISE
IBF
OBF
IBOV
PSPMODE
PORTE Data Direction bits
0000 -111
Legend:
x
= unknown, u = unchanged, – = unimplemented read as ‘0’. Shaded cells are not used by PORTD.
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