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參數(shù)資料
| 型號(hào)： | ENC424J600-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 151/168頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ETHERNET CTRLR W/SPI 44-TQFP |
| 視頻文件： | Fast 100 Mbps Ethernet PICtail Plus Overview |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 控制器類型： | 以太網(wǎng)控制器（IEEE 802.3） |
| 接口： | SPI |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 96mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-TQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 684 (CN2011-ZH PDF) |
| 配用： | AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET |
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2007 Microchip Technology Inc.
DS39599G-page 81
PIC18F2220/2320/4220/4320
7.0
DATA EEPROM MEMORY
The data EEPROM is readable and writable during nor-
mal operation over the entire VDD range. The data
memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).
There are four SFRs used to read and write the
program and data EEPROM memory. These registers
are:
EECON1
EECON2
EEDATA
EEADR
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed.
These devices have 256 bytes of data EEPROM with
an address range from 00h to FFh.
The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write). The
write time is controlled by an on-chip timer. The write time
will vary with voltage and temperature, as well as from
chip to chip. Please refer to parameter D122 (Table 26-1
in Section 26.0 “Electrical Characteristics”) for exact
limits.
7.1
EEADR
The address register can address 256 bytes of data
EEPROM.
7.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit EEPGD determines if the access will be to
program or data EEPROM memory. When clear, oper-
ations will access the data EEPROM memory. When
set, program memory is accessed.
Control bit, CFGS, determines if the access will be to
the Configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access Configuration registers. When CFGS is clear,
the EEPGD bit selects either Flash program or data
EEPROM memory.
The WREN bit enables and disables erase and write
operations. When set, erase and write operations are
allowed. When clear, erase and write operations are
disabled; the WR bit cannot be set while the WREN bit
is clear. This mechanism helps to prevent accidental
writes to memory due to errant (unexpected) code
execution.
Firmware should keep the WREN bit clear at all times
except when starting erase or write operations. Once
firmware has set the WR bit, the WREN bit may be
cleared. Clearing the WREN bit will not affect the
operation in progress.
The WRERR bit is set when a write operation is inter-
rupted by a Reset. In these situations, the user can
check the WRERR bit and rewrite the location. It is nec-
essary to reload the data and address registers
(EEDATA and EEADR), as these registers have
cleared as a result of the Reset.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “Table Reads
and Table Writes” regarding table reads.
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when write is complete. It must be
cleared in software.
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