參數(shù)資料
型號： ENC424J600-I/PT
廠商： Microchip Technology
文件頁數(shù)： 19/168頁
文件大?。?/td> 0K
描述： IC ETHERNET CTRLR W/SPI 44-TQFP
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標(biāo)準(zhǔn)包裝： 160
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-TQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 托盤
產(chǎn)品目錄頁面： 684 (CN2011-ZH PDF)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
2007 Microchip Technology Inc.
DS39599G-page 113
PIC18F2220/2320/4220/4320
TABLE 10-9:
PORTE FUNCTIONS
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit#
Buffer Type
Function
RE0/AN5/RD
bit 0
ST/TTL(1)
Input/output port pin, analog input or read control input in Parallel Slave
Port mode.
For RD (PSP Control mode):
1 = PSP is Idle
0 = Read operation. Reads PORTD register (if chip selected).
RE1/AN6/WR
bit 1
ST/TTL(1)
Input/output port pin, analog input or write control input in Parallel
Slave Port mode.
For WR (PSP Control mode):
1 = PSP is Idle
0 = Write operation. Writes PORTD register (if chip selected).
RE2/AN7/CS
bit 2
ST/TTL(1)
Input/output port pin, analog input or chip select control input in Parallel
Slave Port mode.
For CS (PSP Control mode):
1 = PSP is Idle
0 = External device is selected
MCLR/VPP/RE3(2)
bit 3
ST
Input only port pin or programming voltage input (if MCLR is disabled);
Master Clear input or programming voltage input (if MCLR is enabled).
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
2: The RE3 port bit is available as an input-only pin only in 40-pin devices and when Master Clear function-
ality is disabled (CONFIG3H<7>=0).
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
PORTE
—
—RE3(1)
RE2
RE1
RE0
---- qxxx
---- quuu
LATE
—
LATE Data Latch Register
---- -xxx
---- -uuu
TRISE
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction bits
0000 -111
ADCON1
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
--00 0000
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends on condition.
Shaded cells are not used by PORTE.
Note 1:
The RE3 port bit is available as an input-only pin only in 40-pin devices and when Master Clear functionality is disabled
(CONFIG3H<7>=0).
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