參數(shù)資料
型號(hào)： ENC624J600-I/PT
廠商： Microchip Technology
文件頁數(shù)： 129/168頁
文件大小： 0K
描述： IC ETHERNET CTRLR W/SPI 64-TQFP
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標(biāo)準(zhǔn)包裝： 160
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 托盤
產(chǎn)品目錄頁面： 684 (CN2011-ZH PDF)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
2007 Microchip Technology Inc.
DS21993C-page 61
PIC16CR7X
REGISTER 9-2:
SSPCON: SYNC SERIAL PORT CONTROL (ADDRESS 14h)
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit
1
= The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0
= No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1
= A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In
Master mode, the overflow bit is not set since each new reception (and transmission) is
initiated by writing to the SSPBUF register.
0
= No overflow
In I2C mode:
1
= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV
is a “don’t care” in Transmit mode. SSPOV must be cleared in software in either mode.
0
= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
1
= Enables serial port and configures SCK, SDO and SDI as serial port pins
0
= Disables serial port and configures these pins as I/O port pins
In I2C mode:
1
= Enables the serial port and configures the SDA and SCL pins as serial port pins
0
= Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1
= Idle state for clock is a high level (Microwire default)
0
= Idle state for clock is a low level (Microwire alternate)
In I2C mode:
SCK release control
1
= Enable clock
0
= Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000
= SPI Master mode, clock = FOSC/4
0001
= SPI Master mode, clock = FOSC/16
0010
= SPI Master mode, clock = FOSC/64
0011
= SPI Master mode, clock = TMR2 output/2
0100
= SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101
= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110
= I2C Slave mode, 7-bit address
0111
= I2C Slave mode, 10-bit address
1011
= I2C Firmware Controlled Master mode (slave Idle)
1110
= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111
= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
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