參數資料
型號: ENC624J600-I/PT
廠商: Microchip Technology
文件頁數: 86/168頁
文件大小: 0K
描述: IC ETHERNET CTRLR W/SPI 64-TQFP
視頻文件: Fast 100 Mbps Ethernet PICtail Plus Overview
標準包裝: 160
控制器類型: 以太網控制器(IEEE 802.3)
接口: SPI
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 96mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP
供應商設備封裝: 64-TQFP(10x10)
包裝: 托盤
產品目錄頁面: 684 (CN2011-ZH PDF)
配用: AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
PIC16CR7X
DS21993C-page 22
2007 Microchip Technology Inc.
2.2.2.4
PIE1 Register
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
Note:
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 2-4:
PIE1: (ADDRESS 8Ch)
R/W-0
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1
= Enables the PSP read/write interrupt
0
= Disables the PSP read/write interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1
= Enables the A/D converter interrupt
0
= Disables the A/D converter interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit
1
= Enables the USART receive interrupt
0
= Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit
1
= Enables the USART transmit interrupt
0
= Disables the USART transmit interrupt
bit 3
SSPIE: Synchronous Serial Port Interrupt Enable bit
1
= Enables the SSP interrupt
0
= Disables the SSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1
= Enables the CCP1 interrupt
0
= Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1
= Enables the TMR2 to PR2 match interrupt
0
= Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1
= Enables the TMR1 overflow interrupt
0
= Disables the TMR1 overflow interrupt
Note 1:
PSPIE is reserved on 28-pin devices; always maintain this bit clear.
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