Note to Tables 1 and 2: (1) The embedded IEEE Std. 1149.1 Joint Test " />
參數(shù)資料
型號: EP20K200EQI240-2N
廠商: Altera
文件頁數(shù): 30/117頁
文件大?。?/td> 0K
描述: IC APEX 20KE FPGA 200K 240-PQFP
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 24
系列: APEX-20K®
LAB/CLB數(shù): 832
邏輯元件/單元數(shù): 8320
RAM 位總計: 106496
輸入/輸出數(shù): 168
門數(shù): 404000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 240-BFQFP
供應(yīng)商設(shè)備封裝: 240-PQFP(32x32)
2
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Note to Tables 1 and 2:
(1)
The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
Additional
Features
Designed for low-power operation
1.8-V and 2.5-V supply voltage (see Table 3)
–MultiVoltTM I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see Table 3)
ESB offering programmable power-saving mode
Note to Table 3:
(1)
APEX 20KE devices can be 5.0-V tolerant by using an external resistor.
Table 2. Additional APEX 20K Device Features
Feature
EP20K300E
EP20K400
EP20K400E
EP20K600E
EP20K1000E EP20K1500E
Maximum system
gates
728,000
1,052,000
1,537,000
1,772,000
2,392,000
Typical gates
300,000
400,000
600,000
1,000,000
1,500,000
LEs
11,520
16,640
24,320
38,400
51,840
ESBs
72
104
152
160
216
Maximum
RAM bits
147,456
212,992
311,296
327,680
442,368
Maximum
macrocells
1,152
1,664
2,432
2,560
3,456
Maximum user I/O
pins
408
502
488
588
708
808
Table 3. APEX 20K Supply Voltages
Feature
Device
EP20K100
EP20K200
EP20K400
EP20K30E
EP20K60E
EP20K100E
EP20K160E
EP20K200E
EP20K300E
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
Internal supply voltage (VCCINT)
2.5 V
1.8 V
MultiVolt I/O interface voltage levels (VCCIO) 2.5 V, 3.3 V, 5.0 V
1.8 V, 2.5 V, 3.3 V, 5.0 V (1)
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