參數(shù)資料
型號: EP20K200EQI240-2N
廠商: Altera
文件頁數(shù): 72/117頁
文件大?。?/td> 0K
描述: IC APEX 20KE FPGA 200K 240-PQFP
產(chǎn)品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 24
系列: APEX-20K®
LAB/CLB數(shù): 832
邏輯元件/單元數(shù): 8320
RAM 位總計: 106496
輸入/輸出數(shù): 168
門數(shù): 404000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 240-BFQFP
供應商設備封裝: 240-PQFP(32x32)
58
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Table 22 shows the JTAG timing parameters and values for APEX 20K
devices.
f For more information, see the following documents:
Generic Testing
Each APEX 20K device is functionally tested. Complete testing of each
configurable static random access memory (SRAM) bit and all logic
functionality ensures 100% yield. AC test measurements for APEX 20K
devices are made under conditions equivalent to those shown in
Figure 32. Multiple test patterns can be used to configure devices during
all stages of the production flow.
Table 22. APEX 20K JTAG Timing Parameters & Values
Symbol
Parameter
Min
Max
Unit
tJCP
TCK
clock period
100
ns
tJCH
TCK
clock high time
50
ns
tJCL
TCK
clock low time
50
ns
tJPSU
JTAG port setup time
20
ns
tJPH
JTAG port hold time
45
ns
tJPCO
JTAG port clock to output
25
ns
tJPZX
JTAG port high impedance to valid output
25
ns
tJPXZ
JTAG port valid output to high impedance
25
ns
tJSSU
Capture register setup time
20
ns
tJSH
Capture register hold time
45
ns
tJSCO
Update register clock to output
35
ns
tJSZX
Update register high impedance to valid output
35
ns
tJSXZ
Update register valid output to high impedance
35
ns
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