- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4374 > EP20K200EQI240-2N (Altera)IC APEX 20KE FPGA 200K 240-PQFP PDF資料下載
參數(shù)資料
| 型號： | EP20K200EQI240-2N |
| 廠商： | Altera |
| 文件頁數(shù)： | 57/117頁 |
| 文件大小： | 0K |
| 描述： | IC APEX 20KE FPGA 200K 240-PQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | APEX-20K® |
| LAB/CLB數(shù)： | 832 |
| 邏輯元件/單元數(shù)： | 8320 |
| RAM 位總計： | 106496 |
| 輸入/輸出數(shù)： | 168 |
| 門數(shù)： | 404000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 240-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 240-PQFP（32x32） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁當(dāng)前第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁
44
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Advanced I/O Standard Support
APEX 20KE IOEs support the following I/O standards: LVTTL,
LVCMOS, 1.8-V I/O, 2.5-V I/O, 3.3-V PCI, PCI-X, 3.3-V AGP, LVDS,
LVPECL, GTL+, CTT, HSTL Class I, SSTL-3 Class I and II, and SSTL-2
Class I and II.
f For more information on I/O standards supported by APEX 20KE
devices, see Application Note 117 (Using Selectable I/O Standards in Altera
Devices).
The APEX 20KE device contains eight I/O banks. In QFP packages, the
banks are linked to form four I/O banks. The I/O banks directly support
all standards except LVDS and LVPECL. All I/O banks can support LVDS
and LVPECL with the addition of external resistors. In addition, one block
within a bank contains circuitry to support high-speed True-LVDS and
LVPECL inputs, and another block within a particular bank supports
high-speed True-LVDS and LVPECL outputs. The LVDS blocks support
all of the I/O standards. Each I/O bank has its own VCCIO pins. A single
device can support 1.8-V, 2.5-V, and 3.3-V interfaces; each bank can
support a different standard independently. Each bank can also use a
separate VREF level so that each bank can support any of the terminated
standards (such as SSTL-3) independently. Within a bank, any one of the
terminated standards can be supported. EP20K300E and larger
APEX 20KE devices support the LVDS interface for data pins (smaller
devices support LVDS clock pins, but not data pins). All EP20K300E and
larger devices support the LVDS interface for data pins up to 155 Mbit per
channel; EP20K400E devices and larger with an X-suffix on the ordering
code add a serializer/deserializer circuit and PLL for higher-speed
support.
Each bank can support multiple standards with the same VCCIO for
output pins. Each bank can support one voltage-referenced I/O standard,
but it can support multiple I/O standards with the same VCCIO voltage
level. For example, when VCCIO is 3.3 V, a bank can support LVTTL,
LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
When the LVDS banks are not used as LVDS I/O banks, they support all
of the other I/O standards. Figure 29 shows the arrangement of the
APEX 20KE I/O banks.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 170-050-172L010 | CONN DB50 CRIMP MALE TIN |
| EP20K200EQI240-2 | IC APEX 20KE FPGA 200K 240-PQFP |
| AMC25DRAS | CONN EDGECARD 50POS .100 R/A DIP |
| IDT70V24L20PFGI | IC SRAM 64KBIT 20NS 100TQFP |
| EPF10K100EQC240-1N | IC FLEX 10KE FPGA 100K 240-PQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP20K200EQI240-3ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K200ERC208-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K200ERC208-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K200ERC208-3ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K200ERC240-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。