參數(shù)資料
型號(hào): EP2AGX260EF29C5N
廠商: Altera
文件頁(yè)數(shù): 13/90頁(yè)
文件大?。?/td> 0K
描述: IC ARRIA II GX FPGA 260K 780FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 4
系列: Arria II GX
LAB/CLB數(shù): 10260
邏輯元件/單元數(shù): 244188
RAM 位總計(jì): 12038144
輸入/輸出數(shù): 372
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 780-BBGA
供應(yīng)商設(shè)備封裝: 780-FBGA(29x29)
1–12
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
December 2013
Altera Corporation
Use the following with Equation 1–1:
RSCAL is the OCT resistance value at power up.
T is the variation of temperature with respect to the temperature at power up.
V is the variation of voltage with respect to the VCCIO at power up.
dR/dT is the percentage change of RSCAL with temperature.
dR/dV is the percentage change of RSCAL with voltage.
Table 1–14 lists the OCT variation with temperature and voltage after power-up
calibration for Arria II GX devices.
Table 1–15 lists the OCT variation with temperature and voltage after power-up
calibration for Arria II GZ devices.
Pin Capacitance
Table 1–16 lists the pin capacitance for Arria II GX devices.
Table 1–14. OCT Variation after Power-up Calibration for Arria II GX Devices
Nominal Voltage VCCIO (V)
dR/dT (%/°C)
dR/dV (%/mV)
3.0
0.262
0.035
2.5
0.234
0.039
1.8
0.219
0.086
1.5
0.199
0.136
1.2
0.161
0.288
Table 1–15. OCT Variation after Power-Up Calibration for Arria II GZ Devices (Note 1)
Nominal Voltage, V
CCIO (V)
dR/dT (%/°C)
dR/dV (%/mV)
3.0
0.189
0.0297
2.5
0.208
0.0344
1.8
0.266
0.0499
1.5
0.273
0.0744
1.2
0.317
0.1241
Note to Table 1–15:
(1) Valid for VCCIO range of ±5% and temperature range of 0° to 85°C.
Table 1–16. Pin Capacitance for Arria II GX Devices
Symbol
Description
Typical
Unit
CIO
Input capacitance on I/O pins, dual-purpose pins (differential I/O, clock,
Rup, Rdn), and dedicated clock input pins
7pF
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