參數(shù)資料
型號: EP4S40G5H40I3
廠商: Altera
文件頁數(shù): 18/82頁
文件大小: 0K
描述: IC STRATIX IV FPGA 530K 1517HBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 3
系列: STRATIX® IV GT
LAB/CLB數(shù): 21248
邏輯元件/單元數(shù): 531200
RAM 位總計(jì): 28033024
輸入/輸出數(shù): 654
電源電壓: 0.92 V ~ 0.98 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1517-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 1517-HBGA(42.5x42.5)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–17
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Transmitter REFCLK
Phase Noise
10 Hz
-50
-50
-50
dBc/Hz
100 Hz
-80
-80
-80
dBc/Hz
1 KHz
-110
-110
-110
dBc/Hz
10 KHz
-120
-120
-120
dBc/Hz
100 KHz
-120
-120
-120
dBc/Hz
1 MHz
-130
-130
-130
dBc/Hz
Transmitter REFCLK
Phase Jitter (rms)
for 100 MHz
REFCLK (3)
10 KHz to
20 MHz
——
3
3
3
ps
RREF
——
2000
±1%
——
2000 ±
1%
——
2000
± 1%
Transceiver Clocks
Calibration block
clock frequency
10
125
10
125
10
125
MHz
fixedclk
clock
frequency
PCIe Receiver
Detect
125
125
125
MHz
reconfig_clk
clock frequency
Dynamic
reconfiguration
clock frequency
2.5/
37.5
—50
2.5/
37.5
—50
2.5/
37.5
—50
Delta time between
reconfig_clks
——
2
2
2
ms
Transceiver block
minimum
power-down
(gxb_powerdown)
pulse width
—1
1
1
s
Receiver
Supported I/O
Standards
1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, LVDS
Data rate (Single
width, non-PMA
Direct) (23)
600
3750
600
3750
600
3750
Mbps
Data rate (Double
width, non-PMA
Direct) (23)
1000
8500
1000
6500
1000
6375
Mbps
Data rate (Single
width, PMA Direct)
600
3250
600
3250
600
3250
Mbps
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 2 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade (1)
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
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