- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19910 > EPC2TI32N (Altera)IC CONFIG DEVICE 1.6MBIT 32-TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | EPC2TI32N |
| 廠商： | Altera |
| 文件頁數(shù)： | 14/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG DEVICE 1.6MBIT 32-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | EPC |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲(chǔ)容量： | 1.6Mb |
| 電源電壓： | 3 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 604 (CN2011-ZH PDF) |
| 其它名稱： | 544-1648 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁
Pin Information
Page 21
Configuration Devices for SRAM-Based LUT Devices
January 2012
Altera Corporation
Pin Information
Table 20 lists the pin functions of the EPC1, EPC2, and EPC1441 devices during device
configuration.
f For more information about pin information of EPC devices, refer to the Enhanced
f For more information about pin information of EPCS devices, refer to the Serial
Table 20. EPC1, EPC2, and EPC1441 Device Pin Functions During Configuration (Part 1 of 3)
Pin Name
Pin Number
Pin Type
Description
8-Pin
PDIP (1)
20-Pin
PLCC
32-Pin
TQFP (2)
DATA
12
31
Output
Serial data output. The DATA pin connects to the DATA0 pin
of the FPGA. DATA is latched into the FPGA on the rising
edge of DCLK.
The DATA pin is tri-stated before configuration and when
the nCS pin is high. After configuration, the EPC2 device
drives DATA high, while the EPC1 and EPC1441 device
tri-state DATA.
DCLK
2
4
2
Bidirectional
Clock output when configuring with a single configuration
device or when the configuration device is the first
(master) device in a chain. Clock input for the next (slave)
configuration devices in a chain. The DCLK pin connects to
the DCLK pin of the FPGA.
Rising edges on DCLK increment the internal address
counter and present the next bit of data on the DATA pin.
The counter is incremented only if the OE input is held
high, the nCS input is held low, and all configuration data
has not been transferred to the target device.
After configuration or when OE is low, the EPC1, EPC2 and
EPC1441 device drive DCLK low.
OE
387
Open-drain
bidirectional
Output enable (active high) and reset (active low). The OE
pin connects to the nSTATUS pin of the FPGA.
A low logic level resets the address counter. A high logic
level enables DATA and the address counter to count. If this
pin is low (reset) during configuration, the internal
oscillator becomes inactive and DCLK drives low. For more
information, refer to “Error Detection Circuitry” on page 9.
The OE pin has an internal programmable 1-k
resistor in
EPC2 devices. If internal pull-up resistors are used, do not
use external pull-up resistors on these pins. You can
disable the internal pull-up resistors through the Disable
nCS
and OE pull-ups on configuration device option.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TNY267GN-TL | IC OFFLINE SWIT OTP OCP HV 8SMD |
| GRM1885C2A361JA01D | CAP CER 360PF 100V 5% NP0 0603 |
| XC17S30AVO8C | IC PROM SER 300K 8-SOIC |
| FMM18DSEH | CONN EDGECARD 36POS .156 EYELET |
| EPC2TI32 | IC CONFIG DEVICE 1.6MBIT 32-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPC3.3SC36-A | 功能描述:DC/DC轉(zhuǎn)換器 50 Watts 3.3 Volts RoHS:否 制造商:Murata 產(chǎn)品: 輸出功率: 輸入電壓范圍:3.6 V to 5.5 V 輸入電壓（標(biāo)稱）: 輸出端數(shù)量:1 輸出電壓（通道 1）:3.3 V 輸出電流（通道 1）:600 mA 輸出電壓（通道 2）: 輸出電流（通道 2）: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體尺寸: |
| EPC30 | 制造商:TDK 制造商全稱:TDK Electronics 功能描述:Ferrite Cores For Power Supply and Signal Transformer EPC Cores |
| EPC300 | 制造商:EPC 制造商全稱:EPC 功能描述:High sensitive photodiodes |
| EPC3001 | 制造商:PCA 制造商全稱:PCA ELECTRONICS INC. 功能描述:Flyback Transformer |
| EPC3005 | 制造商:PCA 制造商全稱:PCA ELECTRONICS INC. 功能描述:Flyback Transformer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。