參數(shù)資料
型號(hào)： EPM2210F324A5N
廠商： ALTERA CORP
元件分類： PLD
英文描述： FLASH PLD, PBGA324
封裝： 19 X 19 MM, 1 MM PITCH, LEAD FREE, FBGA-324
文件頁數(shù)： 61/108頁
文件大?。?/td> 1342K
代理商： EPM2210F324A5N
3–6
Core Version a.b.c variable
Altera Corporation
MAX II Device Handbook, Volume 1
December 2007
In System Programmability
programming, the I/O pins are tri-stated and weakly pulled-up to VCCIO
to eliminate board conflicts. The in-system programming clamp and real-
time ISP feature allow user control of I/O state or behavior during ISP.
For more information, refer to “In-System Programming Clamp” on
These devices also offer an ISP_DONE bit that provides safe operation
when in-system programming is interrupted. This ISP_DONE bit, which
is the last bit programmed, prevents all I/O pins from driving until the
bit is programmed.
IEEE 1532 Support
The JTAG circuitry and ISP instruction set in MAX II devices is compliant
to the IEEE 1532-2002 programming specification. This provides
industry-standard hardware and software for in-system programming
among multiple vendor programmable logic devices (PLDs) in a JTAG
chain.
The MAX II 1532 BSDL files will be released on the Altera website when
available.
Jam Standard Test and Programming Language (STAPL)
The Jam STAPL JEDEC standard, JESD71, can be used to program MAX II
devices with in-circuit testers, PCs, or embedded processors. The Jam
byte code is also supported for MAX II devices. These software
programming protocols provide a compact embedded solution for
programming MAX II devices.
f
For more information, refer to the Using Jam STAPL for ISP via an
Embedded Processor chapter in the MAX II Device Handbook.
Programming Sequence
During in-system programming, 1532 instructions, addresses, and data
are shifted into the MAX II device through the TDI input pin. Data is
shifted out through the TDO output pin and compared against the
expected data. Programming a pattern into the device requires the
following six ISP steps. A stand-alone verification of a programmed
pattern involves only stages 1, 2, 5, and 6. These steps are automatically
executed by third-party programmers, the Quartus II software, or the Jam
STAPL and Jam Byte-Code Players.
1.
Enter ISP—The enter ISP stage ensures that the I/O pins transition
smoothly from user mode to ISP mode.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM2210F324C3 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 272 IO RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210F324C3N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 272 IO RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210F324C4 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 272 IO RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210F324C4N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 272 IO RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM2210F324C5 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 272 IO RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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