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參數(shù)資料
| 型號(hào)： | EPM7032BTI44-5 |
| 廠商： | Altera |
| 文件頁(yè)數(shù)： | 16/66頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MAX 7000 CPLD 32 44-TQFP |
| 標(biāo)準(zhǔn)包裝： | 480 |
| 系列： | MAX® 7000B |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 5.0ns |
| 電壓電源 - 內(nèi)部： | 2.375 V ~ 2.625 V |
| 邏輯元件/邏輯塊數(shù)目： | 2 |
| 宏單元數(shù)： | 32 |
| 門數(shù)： | 600 |
| 輸入/輸出數(shù)： | 36 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-TQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
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Altera Corporation
23
MAX 7000B Programmable Logic Device Data Sheet
Open-Drain Output Option
MAX 7000B devices provide an optional open-drain (equivalent to
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (e.g., interrupt and
write enable signals) that can be asserted by any of several devices. It can
also provide an additional wired-OR plane.
Programmable Ground Pins
Each unused I/O pin on MAX 7000B devices may be used as an additional
ground pin. This programmable ground feature does not require the use
of the associated macrocell; therefore, the buried macrocell is still
available for user logic.
Slew-Rate Control
The output buffer for each MAX 7000B I/O pin has an adjustable output
slew rate that can be configured for low-noise or high-speed performance.
A faster slew rate provides high-speed transitions for high-performance
systems. However, these fast transitions may introduce noise transients
into the system. A slow slew rate reduces system noise, but adds a
nominal delay of 4 to 5 ns. When the configuration cell is turned off, the
slew rate is set for low-noise performance. Each I/O pin has an individual
EEPROM bit that controls the slew rate, allowing designers to specify the
slew rate on a pin-by-pin basis. The slew rate control affects both the rising
and falling edges of the output signal.
Advanced I/O Standard Support
The MAX 7000B I/O pins support the following I/O standards: LVTTL,
LVCMOS, 1.8-V I/O, 2.5-V I/O, GTL+, SSTL-3 Class I and II, and SSTL-2
Class I and II.
Table 10. MAX 7000B MultiVolt I/O Support
VCCIO (V)
Input Signal (V)
Output Signal (V)
1.8
2.5
3.3
5.0
1.8
2.5
3.3
5.0
1.8
vv
v
2.5
vv
v
3.3
vv
v
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM7032BUC49-3 | 制造商:Altera Corporation 功能描述:IC MAX |
| EPM7032BUC49-3N | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 32 Macro 41 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM7032BUC49-5 | 制造商:Altera Corporation 功能描述:CPLD MAX 7000B Family 600 Gates 32 Macro Cells 212.8MHz 2.5V 49-Pin UFBGA 制造商:Altera Corporation 功能描述:IC MAX |
| EPM7032BUC49-7 | 制造商:Altera Corporation 功能描述:IC MAX |
| EPM7032JC44-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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