參數(shù)資料
型號: EPM7032BTI44-5
廠商: Altera
文件頁數(shù): 4/66頁
文件大小: 0K
描述: IC MAX 7000 CPLD 32 44-TQFP
標準包裝: 480
系列: MAX® 7000B
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 5.0ns
電壓電源 - 內(nèi)部: 2.375 V ~ 2.625 V
邏輯元件/邏輯塊數(shù)目: 2
宏單元數(shù): 32
門數(shù): 600
輸入/輸出數(shù): 36
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應商設備封裝: 44-TQFP(10x10)
包裝: 托盤
12
Altera Corporation
MAX 7000B Programmable Logic Device Data Sheet
Figure 5. MAX 7000B PIA Routing
While the routing delays of channel-based routing schemes in masked or
field-programmable gate arrays (FPGAs) are cumulative, variable, and
path-dependent, the MAX 7000B PIA has a predictable delay. The PIA
makes a design’s timing performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or VCC. Figure 6 shows the I/O
control block for MAX 7000B devices. The I/O control block has
six or ten global output enable signals that are driven by the true or
complement of two output enable signals, a subset of the I/O pins, or a
subset of the I/O macrocells.
To LAB
PIA Signals
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