參數(shù)資料
型號: EPM7032BTI44-5
廠商: Altera
文件頁數(shù): 17/66頁
文件大?。?/td> 0K
描述: IC MAX 7000 CPLD 32 44-TQFP
標(biāo)準(zhǔn)包裝: 480
系列: MAX® 7000B
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 5.0ns
電壓電源 - 內(nèi)部: 2.375 V ~ 2.625 V
邏輯元件/邏輯塊數(shù)目: 2
宏單元數(shù): 32
門數(shù): 600
輸入/輸出數(shù): 36
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應(yīng)商設(shè)備封裝: 44-TQFP(10x10)
包裝: 托盤
24
Altera Corporation
MAX 7000B Programmable Logic Device Data Sheet
MAX 7000B devices contain two I/O banks. Both banks support all
standards. Each I/O bank has its own VCCIO pins. A single device can
support 1.8-V, 2.5-V, and 3.3-V interfaces; each bank can support a
different standard independently. Within a bank, any one of the
terminated standards can be supported.
Figure 9 shows the arrangement of the MAX 7000B I/O banks.
Figure 9. MAX 7000B I/O Banks for Various Advanced I/O Standards
Table 11 shows which macrocells have pins in each I/O bank.
Each MAX 7000B device has two VREF pins. Each can be set to a separate
VREF level. Any I/O pin that uses one of the voltage-referenced standards
(GTL+, SSTL-2, or SSTL-3) may use either of the two VREF pins. If these
pins are not required as VREF pins, they may be individually
programmed to function as user I/O pins.
Table 11. Macrocell Pins Contained in Each I/O Bank
Device
Bank 1
Bank 2
EPM7032B
1-16
17-32
EPM7064B
1-32
33-64
EPM7128B
1-64
65-128
EPM7256B
1-128, 177-181
129-176, 182-256
EPM7512B
1-265
266-512
Individual
Power Bus
Programmable I/O Banks
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