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參數(shù)資料
| 型號： | EPM7032BTI44-5 |
| 廠商： | Altera |
| 文件頁數(shù)： | 34/66頁 |
| 文件大小： | 0K |
| 描述： | IC MAX 7000 CPLD 32 44-TQFP |
| 標準包裝： | 480 |
| 系列： | MAX® 7000B |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 5.0ns |
| 電壓電源 - 內(nèi)部： | 2.375 V ~ 2.625 V |
| 邏輯元件/邏輯塊數(shù)目： | 2 |
| 宏單元數(shù)： | 32 |
| 門數(shù)： | 600 |
| 輸入/輸出數(shù)： | 36 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-TQFP |
| 供應商設備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
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4
Altera Corporation
MAX 7000B Programmable Logic Device Data Sheet
Notes:
(1)
When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O
pins become JTAG pins.
(2)
Contact Altera for up-to-date information on available device package options.
(3)
All 0.8-mm Ultra FineLine BGA packages are footprint-compatible via the SameFrameTM pin-out feature. Therefore,
designers can design a board to support a variety of devices, providing a flexible migration path across densities
and pin counts. Device migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on
page 14 for more details.
(4)
All FineLine BGA packages are footprint-compatible via the SameFrame pin-out feature. Therefore, designers can
design a board to support a variety of devices, providing a flexible migration path across densities and pin counts.
Device migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 14 for more
details.
MAX 7000B devices use CMOS EEPROM cells to implement logic
functions. The user-configurable MAX 7000B architecture accommodates
a variety of independent combinatorial and sequential logic functions.
The devices can be reprogrammed for quick and efficient iterations
during design development and debug cycles, and can be programmed
and erased up to 100 times.
MAX 7000B devices contain 32 to 512 macrocells that are combined into
groups of 16 macrocells, called logic array blocks (LABs). Each macrocell
has a programmable-AND/fixed-OR array and a configurable register with
independently programmable clock, clock enable, clear, and preset
functions. To build complex logic functions, each macrocell can be
supplemented with both shareable expander product terms and high-
speed parallel expander product terms to provide up to 32 product terms
per macrocell.
Table 3. MAX 7000B Maximum User I/O Pins
Device
44-Pin
PLCC
44-Pin
TQFP
48-Pin
TQFP
49-Pin
0.8-mm
Ultra
FineLine
BGA (3)
100-
Pin
TQFP
100-Pin
FineLine
BGA (4)
144-
Pin
TQFP
169-Pin
0.8-mm
Ultra
FineLine
BGA (3)
208-
Pin
PQFP
256-
Pin
BGA
256-Pin
FineLine
BGA (4)
EPM7032B
36
EPM7064B
36
40
41
68
EPM7128B
41
84
100
EPM7256B
84
120
141
164
EPM7512B
120
141
176
212
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EPM7032BUC49-3 | 制造商:Altera Corporation 功能描述:IC MAX |
| EPM7032BUC49-3N | 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX 7000 32 Macro 41 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM7032BUC49-5 | 制造商:Altera Corporation 功能描述:CPLD MAX 7000B Family 600 Gates 32 Macro Cells 212.8MHz 2.5V 49-Pin UFBGA 制造商:Altera Corporation 功能描述:IC MAX |
| EPM7032BUC49-7 | 制造商:Altera Corporation 功能描述:IC MAX |
| EPM7032JC44-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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