參數(shù)資料
型號: EPM7032QC44-15
廠商: Altera
文件頁數(shù): 66/66頁
文件大?。?/td> 0K
描述: IC MAX 7000 CPLD 32 44-PQFP
產(chǎn)品變化通告: MAX 7000 Series Obsolescence 08/Jun/2009
標準包裝: 576
系列: MAX® 7000
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 15.0ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
邏輯元件/邏輯塊數(shù)目: 2
宏單元數(shù): 32
門數(shù): 600
輸入/輸出數(shù): 36
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-QFP
供應商設備封裝: 44-PQFP(10x10)
包裝: 托盤
其它名稱: 544-2292
Altera Corporation
9
MAX 7000 Programmable Logic Device Family Data Sheet
Each LAB is fed by the following signals:
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Direct input paths from I/O pins to the registers that are used
for fast setup times for MAX 7000E and MAX 7000S devices
Macrocells
The MAX 7000 macrocell can be individually configured for either
sequential or combinatorial logic operation. The macrocell consists
of three functional blocks: the logic array, the product-term select
matrix, and the programmable register. The macrocell of EPM7032,
EPM7064, and EPM7096 devices is shown in Figure 3.
Figure 3. EPM7032, EPM7064 & EPM7096 Device Macrocell
Product-
Ter
T
T m
Select
Matrix
36 Signals
from PIA
16 Expander
Product Ter
T
T ms
Logic Array
Parallel Logic
Expanders
(from other
macrocells)
Shared Logic
Expanders
Clear
Select
Global
Clear
Global
Clocks
Clock/
Enable
Select
2
PRN
CLRN
D/T
Q
ENA
Register
Bypass
To I/O
Control
Block
to PIA
Programmable
Register
From
I/O pin
Fast Input
Select
VCC
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EPM7032SLC44-10 功能描述:IC MAX 7000 CPLD 32 44-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD(復雜可編程邏輯器件) 系列:MAX® 7000 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP(28x28) 包裝:托盤