參數(shù)資料
型號： EPM7256SRI208-10
廠商： Altera
文件頁數(shù)： 14/66頁
文件大?。?/td> 0K
描述： IC MAX 7000 CPLD 256 208-RQFP
產(chǎn)品變化通告： Package Change 30/Jun/2010
標(biāo)準(zhǔn)包裝： 24
系列： MAX® 7000
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1)： 10.0ns
電壓電源 - 內(nèi)部： 4.5 V ~ 5.5 V
邏輯元件/邏輯塊數(shù)目： 16
宏單元數(shù)： 256
門數(shù)： 5000
輸入/輸出數(shù)： 164
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 208-BFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 208-RQFP（28x28）
包裝： 托盤
產(chǎn)品目錄頁面： 604 (CN2011-ZH PDF)
其它名稱： 544-2070
EPM7256SRI208-10-ND
Altera Corporation
21
MAX 7000 Programmable Logic Device Family Data Sheet
By using an external 5.0-V pull-up resistor, output pins on MAX
7000S devices can be set to meet 5.0-V CMOS input voltages. When
VCCIO is 3.3 V, setting the open drain option will turn off the output
pull-up transistor, allowing the external pull-up resistor to pull the
output high enough to meet 5.0-V CMOS input voltages. When
VCCIO is 5.0 V, setting the output drain option is not necessary
because the pull-up transistor will already turn off when the pin
exceeds approximately 3.8 V, allowing the external pull-up resistor to
pull the output high enough to meet 5.0-V CMOS input voltages.
Slew-Rate Control
The output buffer for each MAX 7000E and MAX 7000S I/O pin has
an adjustable output slew rate that can be configured for low-noise
or high-speed performance. A faster slew rate provides high-speed
transitions for high-performance systems. However, these fast
transitions may introduce noise transients into the system. A slow
slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns.
In MAX 7000E devices, when the Turbo Bit is turned off, the slew
rate is set for low noise performance. For MAX 7000S devices, each
I/O pin has an individual EEPROM bit that controls the slew rate,
allowing designers to specify the slew rate on a pin-by-pin basis.
Programming with
External Hardware
MAX 7000 devices can be programmed on Windows-based PCs with
the Altera Logic Programmer card, the Master Programming Unit
(MPU), and the appropriate device adapter. The MPU performs a
continuity check to ensure adequate electrical contact between the
adapter and the device.
f For more information, see the Altera Programming Hardware Data
The Altera development system can use text- or waveform-format
test vectors created with the Text Editor or Waveform Editor to test
the programmed device. For added design verification, designers
can perform functional testing to compare the functional behavior of
a MAX 7000 device with the results of simulation. Moreover, Data
I/O, BP Microsystems, and other programming hardware
manufacturers also provide programming support for Altera
devices.
f For more information, see the Programming Hardware Manufacturers.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7256SRI208-10N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 256 Macro 164 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7256WC208-20 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD
EPM7256WC208-25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD
EPM7384AEFC256-10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
EPM7384AEFC256-12 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
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