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參數(shù)資料
| 型號： | EPM7256SRI208-10 |
| 廠商： | Altera |
| 文件頁數(shù)： | 21/66頁 |
| 文件大小： | 0K |
| 描述： | IC MAX 7000 CPLD 256 208-RQFP |
| 產(chǎn)品變化通告： | Package Change 30/Jun/2010 |
| 標準包裝： | 24 |
| 系列： | MAX® 7000 |
| 可編程類型： | 系統(tǒng)內可編程 |
| 最大延遲時間 tpd(1)： | 10.0ns |
| 電壓電源 - 內部： | 4.5 V ~ 5.5 V |
| 邏輯元件/邏輯塊數(shù)目： | 16 |
| 宏單元數(shù)： | 256 |
| 門數(shù)： | 5000 |
| 輸入/輸出數(shù)： | 164 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BFQFP 裸露焊盤 |
| 供應商設備封裝： | 208-RQFP（28x28） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 604 (CN2011-ZH PDF) |
| 其它名稱： | 544-2070 EPM7256SRI208-10-ND |
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28
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
(2)
Minimum DC input voltage on I/O pins is –0.5 V and on 4 dedicated input pins is –0.3 V. During transitions, the
inputs may undershoot to –2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than
20 ns.
(3)
Numbers in parentheses are for industrial-temperature-range devices.
(4)
VCC must rise monotonically.
(5)
The POR time for all 7000S devices does not exceed 300 μs. The sufficient VCCINT voltage level for POR is 4.5 V. The
device is fully initialized within the POR time after VCCINT reaches the sufficient POR voltage level.
(6)
3.3-V I/O operation is not available for 44-pin packages.
(7)
The VCCISP parameter applies only to MAX 7000S devices.
(8)
During in-system programming, the minimum DC input voltage is –0.3 V.
(9)
These values are specified under the MAX 7000 recommended operating conditions in Table 14 on page 26.
(10) The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH parameter refers
to high-level TTL or CMOS output current.
(11) The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to
low-level TTL, PCI, or CMOS output current.
(12) When the JTAG interface is enabled in MAX 7000S devices, the input leakage current on the JTAG pins is typically
–60 μA.
(13) Capacitance is measured at 25° C and is sample-tested only. The OE1 pin has a maximum capacitance of 20 pF.
Figure 11 shows the typical output drive characteristics of MAX 7000
devices.
Figure 11. Output Drive Characteristics of 5.0-V MAX 7000 Devices
Timing Model
MAX 7000 device timing can be analyzed with the Altera software, with a
variety of popular industry-standard EDA simulators and timing
analyzers, or with the timing model shown in Figure 12. MAX 7000
devices have fixed internal delays that enable the designer to determine
the worst-case timing of any design. The Altera software provides timing
simulation, point-to-point delay prediction, and detailed timing analysis
for a device-wide performance evaluation.
VO Output Voltage (V)
12345
30
60
90
150
120
VCCIO = 3.3 V
IOL
IOH
Room Temperature
3.3
VO Output Voltage (V)
12345
30
60
90
150
120
VCCIO = 5.0 V
IOL
IOH
Room Temperature
I O
Typical
Output
Current (mA)
I O
Typical
Output
Current (mA)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EPM7256SRI208-10N | 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX 7000 256 Macro 164 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM7256WC208-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD |
| EPM7256WC208-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD |
| EPM7384AEFC256-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| EPM7384AEFC256-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
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