Notes to tables: (1) These values are specified under the recommende" />
參數(shù)資料
型號(hào)： EPM7256SRI208-10
廠商： Altera
文件頁(yè)數(shù)： 49/66頁(yè)
文件大?。?/td> 0K
描述： IC MAX 7000 CPLD 256 208-RQFP
產(chǎn)品變化通告： Package Change 30/Jun/2010
標(biāo)準(zhǔn)包裝： 24
系列： MAX® 7000
可編程類(lèi)型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 10.0ns
電壓電源 - 內(nèi)部： 4.5 V ~ 5.5 V
邏輯元件/邏輯塊數(shù)目： 16
宏單元數(shù)： 256
門(mén)數(shù)： 5000
輸入/輸出數(shù)： 164
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 208-BFQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 208-RQFP（28x28）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 604 (CN2011-ZH PDF)
其它名稱： 544-2070
EPM7256SRI208-10-ND
Altera Corporation
53
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more
information on switching waveforms.
(2)
This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter
must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal
path.
(3)
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(4)
These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5)
The fMAX values represent the highest frequency for pipelined data.
(6)
Operating conditions: VCCIO = 3.3 V ± 10% for commercial and industrial use.
(7)
For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8)
The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells
running in the low-power mode.
Power
Consumption
Supply power (P) versus frequency (fMAX in MHz) for MAX 7000 devices
is calculated with the following equation:
P = PINT + PIO = ICCINT × VCC + PIO
The PIO value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
The ICCINT value, which depends on the switching frequency and the
application logic, is calculated with the following equation:
ICCINT =
A × MCTON + B × (MCDEV – MCTON) + C × MCUSED × fMAX × togLC
The parameters in this equation are shown below:
MCTON
= Number of macrocells with the Turbo Bit option turned on,
as reported in the MAX+PLUS II Report File (.rpt)
MCDEV
= Number of macrocells in the device
MCUSED = Total number of macrocells in the design, as reported
in the MAX+PLUS II Report File (.rpt)
fMAX
= Highest clock frequency to the device
togLC
= Average ratio of logic cells toggling at each clock
(typically 0.125)
A, B, C
= Constants, shown in Table 39
相關(guān)PDF資料
PDF描述
VI-2WX-CY-F2 CONVERTER MOD DC/DC 5.2V 50W
TAP105M035HSB CAP TANT 1UF 35V 20% RADIAL
ABM30DTAS CONN EDGECARD 60POS R/A .156 SLD
EPM7512AETC144-12N IC MAX 7000 CPLD 512 144-TQFP
ISL61851DIBZ IC USB PWR CTRLR DUAL 8SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7256SRI208-10N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 256 Macro 164 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7256WC208-20 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD
EPM7256WC208-25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD
EPM7384AEFC256-10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
EPM7384AEFC256-12 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*