參數(shù)資料
型號(hào): EPM9560RI240-20
廠商: Altera
文件頁數(shù): 42/46頁
文件大小: 0K
描述: IC MAX 9000 CPLD 560 240-RQFP
產(chǎn)品變化通告: Package Change 30/Jun/2010
標(biāo)準(zhǔn)包裝: 24
系列: Max® 9000
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 20.0ns
電壓電源 - 內(nèi)部: 4.5 V ~ 5.5 V
邏輯元件/邏輯塊數(shù)目: 35
宏單元數(shù): 560
門數(shù): 12000
輸入/輸出數(shù): 191
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 240-BFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 240-RQFP(32x32)
包裝: 托盤
其它名稱: 544-2367
Altera Corporation
5
MAX 9000 Programmable Logic Device Family Data Sheet
The MAX 9000 family is supported by Altera’s MAX+PLUS II
development system, a single, integrated software package that offers
schematic, text—including VHDL, Verilog HDL, and the Altera
Hardware Description Language (AHDL)—and waveform design entry,
compilation and logic synthesis, simulation and timing analysis, and
device programming. The MAX+PLUS II software provides EDIF 2 0 0
and 3 0 0, LPM, and other interfaces for additional design entry and
simulation support from other industry-standard PC- and UNIX-
workstation-based EDA tools. The MAX+PLUS II software runs on
Windows-based PCs as well as Sun SPARCstation, HP 9000 Series
700/800, and IBM RISC System/6000 workstations.
f For more information on development tools, see the MAX+PLUS II
Functional
Description
MAX 9000 devices use a third-generation MAX architecture that yields
both high performance and a high degree of utilization for most
applications. The MAX 9000 architecture includes the following elements:
Logic array blocks
Macrocells
Expander product terms (shareable and parallel)
FastTrack Interconnect
Dedicated inputs
I/O cells
Figure 1 shows a block diagram of the MAX 9000 architecture.
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