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| 型號： | EVAL-AD1940MINIBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD1940 MINI SIGMADSP |
| 標準包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻，音頻處理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | AD1940 |
| 主要屬性： | 單芯片多通道 28/56 位音頻 DSP |
| 次要屬性： | 均衡，交叉，低音增強，多頻帶動態(tài)處理，延遲等 |
| 已供物品： | 板，線纜，CD，電源，USB 適配器 |
| 產(chǎn)品目錄頁面： | 775 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD1940YSTZ-ND - IC DSP AUDIO 16CH/28BIT 48-LQFP AD1940YSTZRL-ND - IC DSP AUDIO 16CH/28BIT 48-LQFP |
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AD1940/AD1941
Rev. B | Page 23 of
36
04607-0-021
TIME (ms)
OU
TPU
T
LEVEL
(
V
)
1
0.8
0.6
0.4
0.2
0
–0.6
–0.4
–0.2
–0.8
–1
35
25
15
5
20
10
0
30
Figure 21. Slew RAM—Constant Time Update Increasing Ramp, Half Scale
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
TIME (ms)
OU
TPU
T
LEVEL
(
V
)
04607-031
35
25
15
5
20
10
030
Figure 22. Slew RAM—Constant Time Update Decreasing Ramp, Full Scale
Constant Time Update Math
Constant time math is accomplished by adding a step value that
is calculated after each new target is loaded. The equation for
this step size is
Step
= (Target Data Slew Data)/(Number of Steps)
Figure 20 shows a plot of the target/slew RAM operating in
constant time mode. For this example, 128 steps are used to
reach the target value. This type of ramping takes a fixed
amount of time for a given number of steps, regardless of the
difference in the initial state and the target value. Figure 21
shows a plot of a constant time ramp from –80 dB to –6 dB (half
scale) using 128 steps. You can see that the ramp takes the same
amount of time as the previous ramp from –80 dB to 0 dB. A
constant time decreasing ramp plot is shown in Figure 21.
SAFELOAD REGISTERS
Many applications require real time control of signal processing
parameters, such as filter coefficients, mixer gains, multichannel
virtualizing parameters, or dynamics processing curves. To
prevent instability from occurring, all of the parameters of a
biquad filter must be updated at the same time. Otherwise, the
filter could execute for one or two audio frames with a mix of
old and new coefficients. This mix could cause temporary
instability, leading to transients that could take a long time to
decay. To eliminate this problem, the AD1940/AD1941 load a
set of 10 registers in the control port (five for 28-bit parameters,
and another five for indirectly addressing the target/slew
RAMs) with the desired parameter or target/slew RAM address
and data. Five registers are used because a biquad filter uses five
coefficients and it is desirable to be able to do a complete
biquad update in one transaction. The safeload registers can be
used to update either the parameter RAM or target/slew RAM
values. Once these registers are loaded, the appropriate initiate
safe transfer bit (there are separate bits for parameter and
target/slew loads) in the core control register should be set to
initiate the loading into RAM. Program lengths should be
limited to 1,531 cycles (1,536 5) to ensure that the SigmaDSP
is able to perform the safeloads. It can be guaranteed that the
safeload will have occurred within one LRCLK period (21 μs at
fs = 48 kHz) of the initiate safe transfer bit being set.
The safeload logic automatically sends only those safeload regis-
ters that have been written to since the last safeload operation.
For example, if only two parameters are to be sent, only two of
the five safeload registers must be written to. When the initial
safe transfer bit (in the core control register) is asserted, only
those two registers are sent; the other three registers are not sent
to the RAM and can still hold old or invalid data.
Table 22. Data Capture Control Registers (2634–2641)
Register Bits
Function
12:2
11-Bit program counter address
1:0
Register select
00 = Mult_X_input
01 = Mult_Y_input
10 = MAC_output
11 = Accum_fback
DATA CAPTURE REGISTERS
The AD1940/AD1941’s data capture feature allows the data at
any node in the signal processing flow to be sent to one of six
control port-readable registers or to a serial output pin. This can
be used to monitor and display information about internal
signal levels or compressor/limiter activity.
The AD1940/AD1941 contain six independent control port-
readable data capture registers, and two digital output
capture registers. The digital output registers are output on
SDATA_OUT7 when the data capture serial out enable bit
(Bit 14) is set in serial output Control Register 2. These reg-
isters are useful when debugging the signal processing flow.
For each of the data capture registers, a capture count and a
register select must be set. The capture count is a number
between 0 and 1,535 that corresponds to the program step
number where the capture occurs. The register select field
programs one of four registers in the DSP core that is
transferred to the data capture register when the program
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