- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16847 > EVAL-AD1940MINIBZ (Analog Devices Inc)BOARD EVAL AD1940 MINI SIGMADSP PDF資料下載
參數(shù)資料
| 型號： | EVAL-AD1940MINIBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD1940 MINI SIGMADSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻，音頻處理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | AD1940 |
| 主要屬性： | 單芯片多通道 28/56 位音頻 DSP |
| 次要屬性： | 均衡，交叉，低音增強(qiáng)，多頻帶動(dòng)態(tài)處理，延遲等 |
| 已供物品： | 板，線纜，CD，電源，USB 適配器 |
| 產(chǎn)品目錄頁面： | 775 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD1940YSTZ-ND - IC DSP AUDIO 16CH/28BIT 48-LQFP AD1940YSTZRL-ND - IC DSP AUDIO 16CH/28BIT 48-LQFP |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
AD1940/AD1941
Rev. B | Page 12 of
36
PIN FUNCTIONS
Table 10 shows the AD1940/AD1941’s pin numbers, names, and
functions. Input pins have a logic threshold compatible with
TTL input levels and may be used in systems with 3.3 V or
5 V logic.
SDATA_IN0
SDATA_IN1
SDATA_IN2/TDM_IN1
SDATA_IN3/TDM_IN0
Serial Data/TDM Inputs. The serial format is selected by
writing to Bits 2:0 of the serial input port control register.
SDATA_IN2 and SDATA_IN3 are dual-function pins that can
be set to a variety of standard 2-channel formats or to TDM
mode. Two of these four pins (SDATA_IN2 and SDATA_IN3)
can be used as TDM inputs in either dual-wire 8-channel mode
or single-wire 16-channel mode (TDM_O0 only). In dual-wire
8-channel mode, Channels 0 to 7 are input on SDATA_IN3 and
Channels 8 to 15 on SDATA_IN2. In single-wire 16-channel
mode, Channels 0 to 15 are input on SDATA_IN2. See the
Serial Data Input/Output Ports section for further explanation.
LRCLK_IN
BCLK_IN
Left/Right and Bit Clocks for Timing the Input Data. These
input clocks are associated with the SDATA_IN0 through
SDATA_IN3 signals. The input port is always in a slave
configuration. These pins also function as frame sync and bit
clock for the input TDM stream.
SDATA_OUT0/TDM_O0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4/TDM_O1
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7/DCSOUT
Serial Data/TDM/Data Capture Outputs. These pins are used
for serial digital outputs. For non-TDM systems, these eight
pins can output 16 channels of digital audio, using a variety of
standard 2-channel formats. They are grouped into two groups
of four pins (Pins 0 to 3 and Pins 4 to 7); each group can be
independently set to any of the available serial modes, allowing
the AD1940/AD1941 to simultaneously communicate with two
external devices with different serial formats. Two of these eight
pins (SDATA_OUT0 and SDATA_OUT4) can be used as TDM
outputs in either dual-wire 8-channel mode or single-wire 16-
channel mode (TDM_OUT0 only). In dual-wire 8-channel
mode, Channels 0 to 7 are output on SDATA_OUT0 and
Channels 8 to 15 on SDATA_OUT4. See the Serial Data
Input/Output Ports section for further explanation.
SDATA_OUT7 can also be used as a data capture output, as
described in the Data Capture Registers section.
LRCLK_OUT0
BCLK_OUT0
Output Clocks. This clock pair is used for outputs
SDATA_OUT0 through SDATA_OUT3. In slave mode, these
clocks are inputs to the AD1940/AD1941. On power-up, these
pins are set to slave mode to avoid conflicts with external
master mode devices.
LRCLK_OUT1
BCLK_OUT1
Output Clocks. This clock pair is used for outputs
SDATA_OUT4 through SDATA_OUT7. In slave mode, these
clocks are inputs to the AD1940/AD1941. On power-up, these
pins are set to slave mode to avoid conflicts with external
master mode devices.
MCLK
Master Clock Input. The AD1940/AD1941 uses a PLL to
generate the appropriate internal clock for the DSP core. An
in-depth description of using the PLL is found in the Setting
Master Clock/PLL Mode section.
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL Mode Control Pins. The functionality of these pins is
described in the Setting Master Clock/PLL Mode section.
CDATA (AD1940)
Serial Data Input for the SPI Control Port.
COUT (AD1940)
Serial Data Output for the SPI Port. This is used for reading
back registers and memory locations. It is three-stated when an
SPI read is not active.
CCLK (AD1940)
SPI Bit Clock. This clock may either run continuously or be
gated off between SPI transactions.
CLATCH (AD1940)
SPI Latch Signal. This must go low at the beginning of an SPI
transaction and high at the end of a transaction. Each SPI
transaction may take a different number of CCLKs to complete,
depending on the address and read/write bit that are sent at the
beginning of the SPI transaction.
SCL (AD1941)
I2C Clock. This pin is always an input because the AD1941
cannot act as a master on the I2C bus. The line connected to this
pin should have a 2 kΩ pull-up resistor on it.
SDA (AD1941)
I2C Serial Data. The data line is bidirectional. The line
connected to this pin should have a 2 kΩ pull-up resistor on it.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADN8830ACPZ | IC CTRLR THERMO COOLER 32-LFCSP |
| MAX674CSA+T | IC VREF SERIES PREC 10V 8-SOIC |
| RSC06DRXN-S734 | CONN EDGECARD 12POS DIP .100 SLD |
| SDR1006-100ML | INDUCTOR POWER 10UH 2.6A SMD |
| AD9520-4/PCBZ | BOARD EVAL FOR AD9520-4 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD1941EB | 制造商:Analog Devices 功能描述:EVAL BD SIGMADSPMULTICHANAUDIO PROCESSOR - Bulk |
| EVAL-AD1953EB | 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk 制造商:Analog Devices 功能描述:EVALUATION KIT ((NS)) |
| EVAL-AD1953EBZ | 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk |
| EVAL-AD1954EB | 制造商:Rochester Electronics LLC 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk 制造商:Analog Devices 功能描述: |
| EVAL-AD1955EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD1955 制造商:Analog Devices 功能描述:EVAL BOARD FOR 24 BIT 192KHZ DAC 120 DB - Bulk 制造商:Rochester Electronics LLC 功能描述:EVAL BOARD FOR 24 BIT 192KHZ DAC 120 DB - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。