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參數(shù)資料
| 型號： | EVAL-AD1940MINIBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD1940 MINI SIGMADSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻，音頻處理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | AD1940 |
| 主要屬性： | 單芯片多通道 28/56 位音頻 DSP |
| 次要屬性： | 均衡，交叉，低音增強(qiáng)，多頻帶動態(tài)處理，延遲等 |
| 已供物品： | 板，線纜，CD，電源，USB 適配器 |
| 產(chǎn)品目錄頁面： | 775 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD1940YSTZ-ND - IC DSP AUDIO 16CH/28BIT 48-LQFP AD1940YSTZRL-ND - IC DSP AUDIO 16CH/28BIT 48-LQFP |
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AD1940/AD1941
Rev. B | Page 11 of
36
FEATURES
The core of the AD1940/AD1941 is a 28-bit DSP (56-bit, double
precision) optimized for audio processing. The parts’ program
RAM can be loaded with a custom program after power-up.
Signal processing parameters are stored in a 1024 location
parameter RAM, which is initialized on power-up by an
internal boot ROM. New values are written to the parameter
RAM using the control port. The values stored in the parameter
RAM control individual signal processing blocks, such as IIR
equali-zation filters, dynamics processors, audio delays, and
mixer levels. A safeload feature allows parameters to be
transparently updated without causing clicks on the output
signals.
The target/slew RAM contains 64 locations and can be used as
channel volume controls or for other parameter updates. These
RAM locations take a target value for a given parameter and
ramp the current parameter value to the new value using a
specified time constant and one of a selection of linear or
logarithmic curves.
The AD1940/AD1941 contain eight independent data capture
circuits that can be programmed to tap the signal flow of the
processor at any point in the DSP algorithm flow. Six of these
captured signals can be accessed by reading from the data
capture registers through the control port. The remaining two
data capture registers can be used to send any internal captured
signal to a stereo digital output signal on Pin SDATA_OUT7 for
driving external DACs or digital analyzers.
The AD1940/AD1941 have a sophisticated control port that
supports complete read/write capability of all memory
locations. Five control registers (Core, RAM configuration,
Serial Output 0 to 7, Serial Output 8 to 15, and serial input) are
provided to offer complete control of the chip’s configuration
and serial modes. Handshaking is included for ease of memory
uploads/downloads. The AD1940 is SPI-controlled and the
AD1941 is controlled by an I2C bus.
The AD1940/AD1941 have very flexible serial data
input/output ports that allow glueless interconnection to a
variety of ADCs, DACs, general-purpose DSPs, S/PDIF
receivers and trans-mitters, and sample rate converters. The
AD1940/AD1941 can be configured in I2S, left-justified, right-
justified, or TDM serial port-compatible modes. It can support
16, 20, and 24 bits in all modes. The AD1940/AD1941 accepts
serial audio data in MSB first and twos complement format.
A master clock phase-locked loop (PLL) allows the AD1940/
AD1941 to be clocked from a variety of different clock speeds.
The PLL can accept inputs of 64 × fS, 256 × fS, 384 × fS, or 512 ×
fS to generate the core’s internal master clock.
The AD1940/AD1941 operate from a single 2.5 V power supply.
An on-board voltage regulator can be used to operate the chip
with 3.3 V or 5 V supplies. They are fabricated on a single
monolithic integrated circuit and are housed in 48-lead
LQFP packages for operation over the –40°C to +105°C
temperature range.
04607-0-003
28
× 28
DSP CORE
DATA FORMAT:
5.23 (SINGLE PRECISION)
10.46 (DOUBLE PRECISION)
VOLTAGE REGULATOR
MEMORY CONTROLLERS
CONTROL
REGISITER
TRAP REG.
SAFELOAD
REGISTER
SERIAL
CONTROL
PORT
MCLK
PLL
DATA MEMORY
6k
× 28
TARGET/SLEW
RAM
64
× 28
SERIAL
DATA/TDM
INPUT
GROUP
PLL MODE
SELECT
MASTER
CLOCK
INPUT
CONTROL PORT
I/O GROUP
RESETB
PROGRAM
RAM
1536
× 40
BOOT
ROM
BOOT
ROM
PARAMETER
RAM
1024
× 28
COEFFICIENT
ROM
512
× 28
2
4
2
SERIAL DATA/
TDM OUTPUT
GROUP
REGULATOR
GROUP
ADDRESS SELECT
Figure 9. Block Diagram
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