Typ1 Max Unit INTERFACE TIMING CHAR" />
參數(shù)資料
型號(hào)： EVAL-AD5204SDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/20頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5204
標(biāo)準(zhǔn)包裝： 1
系列： *
AD5204/AD5206
Rev. C | Page 4 of 20
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
INTERFACE TIMING CHARACTERISTICS7, 11, 12
Input Clock Pulse Width
tCH, tCL
Clock level high or low
20
ns
Data Setup Time
tDS
5
ns
Data Hold Time
tDH
5
ns
CLK-to-SDO Propagation Delay13
tPD
RL = 2 kΩ , CL < 20 pF
1
150
ns
CS Setup Time
tCSS
15
ns
CS High Pulse Width
tCSW
40
ns
Reset Pulse Width
tRS
90
ns
CLK Fall to CS Fall Setup
tCSH0
0
ns
CLK Fall to CS Rise Hold Time
tCSH1
0
ns
CS Rise to Clock Rise Setup
tCS1
10
ns
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Applies to all VRs.
3 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from the ideal position between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 28.
IW = VDD/R for both VDD = 3 V and VDD = 5 V.
4 VAB = VDD, wiper (VW) = no connect.
5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic at operating conditions. See the test circuit in Figure 27.
6 Resistor Terminal A, Terminal B, and Wiper W have no limitations on polarity with respect to each other.
7 Guaranteed by design and not subject to production test.
8 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All dynamic characteristics use VDD = 5 V.
11 Applies to all parts.
12 See the timing diagrams (Figure 3 to Figure 5) for the location of the measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V)
and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 5 V.
13 The propagation delay depends on the values of VDD, RL, and CL (see the Operation section).
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