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| 型號(hào)： | EVAL-AD5204SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5204 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
AD5204/AD5206
Rev. C | Page 15 of 20
DIGITAL INTERFACING
The AD5204/AD5206 each contain a standard 3-wire serial
input control interface. The three inputs are clock (CLK), chip
select input (CS), and serial data input (SDI). The positive-
edge-sensitive CLK input requires clean transitions to avoid
clocking incorrect data into the serial input register. Standard
logic families work well. If mechanical switches are used for
product evaluation, they should be debounced by a flip-flop or
by other suitable means.
shows more detail of the
internal digital circuitry. When
CS is taken active low, the clock
loads data into the serial register on each positive clock edge
(see
). When using a positive (VDD) and negative (VSS)
supply voltage, the logic levels are still referenced to digital
ground (GND).
The serial data output (SDO) pin contains an open-drain
n-channel FET. This output requires a pull-up resistor to transfer
data to the SDI pin of the next package. The pull-up resistor
termination voltage can be larger than the VDD supply of the
AD5204. For example, the AD5204 can operate at VDD = 3.3 V,
and the pull-up for the interface to the next device can be set at
5 V. This allows for daisy chaining several RDACs from a
single-processor serial data line.
If a pull-up resistor is used to connect the SDI pin of the
next device in the series, the clock period must be increased.
Capacitive loading at the daisy-chain node (where SDO and
SDI are connected) between the devices must be accounted for
to successfully transfer data. When daisy chaining is used, the
CS should be kept low until all the bits of every package are
clocked into their respective serial registers, ensuring that the
address bits and data bits are in the proper decoding locations.
This requires 22 bits of address and data complying to the data-
word format outlined in
if two AD5204 4-channel RDACs
are daisy-chained. During shutdown (
SHDN), the SDO output
pin is forced to the off (logic high state) position to disable power
dissipation in the pull-up resistor. See
for the equivalent
SDO output circuit schematic.
Table 9. Input Logic Control Truth Table1
CLK
CS
PR
SHDN
Register Activity
L
H
No SR effect; enables SDO pin.
P
L
H
Shift one bit in from the SDI pin. The
11th bit entered is shifted out of the
SDO pin.
X
P
H
Load SR data into the RDAC latch
based on A2, A1, A0 decode (Table 10).
X
H
No operation.
X
L
H
Sets all RDAC latches to midscale;
wiper centered and SDO latch
cleared.
X
H
P
H
Latches all RDAC latches to 0x80.
X
H
L
Open circuits all A resistor terminals,
connects Wiper W to Terminal B, and
turns off the SDO output transistor.
1 P = positive edge, X = don’t care, SR = shift register.
Table 10. Address Decode Table
A2
A1
A0
Latch Decoded
0
RDAC 1
0
1
RDAC 2
0
1
0
RDAC 3
0
1
RDAC 4
1
0
RDAC 5 AD5206 only
1
0
1
RDAC 6 AD5206 only
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 11 bits of
the data-word entered into the serial register are held when CS
returns high. When CS goes high, the address decoder is gated,
enabling one of four or six positive-edge-triggered RDAC
latches (see
for details).
ADDR
DECODE
RDAC 1
RDAC 2
RDAC 4/
RDAC 6
SERIAL
REGISTER
AD5204/AD5206
SDI
CLK
CS
06
88
4-
04
8
Figure 23. Equivalent Input Control Logic
The target RDAC latch is loaded with the last eight bits of the
serial data-word, completing one DAC update. Four separate
8-bit data-words must be clocked in to change all four VR
settings.
SERIAL
REGISTER
SDI
CK RS
D
SHDN
CS
CLK
PR
SDO
GND
Q
06
88
4-
0
49
Figure 24. Detail SDO Output Schematic of the AD5204
All digital pins (CS, SDI, SDO, PR, SHDN, and CLK) are
protected with a series input resistor and a parallel Zener ESD
structure (see
).
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