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| 型號： | EVAL-AD5204SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5204 |
| 標準包裝： | 1 |
| 系列： | * |
AD5204/AD5206
Rev. C | Page 12 of 20
OPERATION
The AD5204 provides a 4-channel, 256-position digitally
controlled VR device, and the AD5206 provides a 6-channel,
256-position digitally controlled VR device. Changing the pro-
grammed VR settings is accomplished by clocking an 11-bit
serial data-word into the SDI pin. The format of this data-word
is three address bits, MSB first, followed by eight data bits, MSB
first. Table 6 provides the serial register data-word format.
Table 6. Serial Data-Word Format
Address
Data
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
MSB
LSB
210
28
27
20
See Table 10 for the AD5204/AD5206 address assignments to
decode the location of the VR latch receiving the serial register
data in Bit B7 through Bit B0. The VR outputs can be changed
one at a time in random sequence. The AD5204 presets to
midscale by asserting the PR pin, simplifying fault condition
recovery at power up. Both parts have an internal power-on
preset that places the wiper in a preset midscale condition at
power on. In addition, the AD5204 contains a power shutdown pin
(SHDN) that places the RDAC in a zero power consumption
state, where terminals Ax are open circuited and wipers Wx are
connected to terminals Bx, resulting in only leakage currents
being consumed in the VR structure. In shutdown mode, the
VR latch settings are maintained so that the VR settings return
to their previous resistance values when the device is returned
to operational mode from power shutdown.
D7
D6
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
Ax
Wx
Bx
RS
SHDN
RS
06
88
4-
0
44
Figure 21. AD5204/AD5206 Equivalent RDAC Circuit
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