參數(shù)資料
型號: EVAL-AD5292EBZ
廠商: Analog Devices Inc
文件頁數(shù): 11/32頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD5292
標(biāo)準(zhǔn)包裝: 1
主要目的: 數(shù)字電位器
嵌入式:
已用 IC / 零件: AD5292
主要屬性: 1 通道,1024 位置
次要屬性: SPI 接口
已供物品: 板,CD
AD5291/AD5292
Rev. D | Page 19 of 32
0
100,000
200,000
300,000
400,000
500,000
600,000
700,000
BANDW
ID
T
H
(
H
z)
800,000
900,000
1,000,000
CODE (Decimal)
512
0
128
64
32
16
8
0
128
256
64
32
16
8
0767
4-
222
20k – 0pF
20k – 75pF
20k – 150pF
20k – 250pF
50k – 0pF
50k – 75pF
50k – 150pF
50k – 250pF
100k – 0pF
100k – 75pF
100k – 150pF
100k – 250pF
AD5292
AD5291
Figure 48. Bandwidth vs Code vs Net Capacitance
07
67
4-
0
34
35
30
25
–5
20
15
10
5
0
–0.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
SU
PPL
Y
C
U
R
EN
T
I
DD
(m
A
)
TIME (ms)
Figure 49. IDD Waveform While Blowing/Reading Fuse
07
67
4-
03
3
35
–5
0
5
10
15
20
25
30
VO
L
T
A
G
E
(
V)
TIME (s)
VWB
, CODE: FULL SCALE,
NORMAL MODE
SYNC
–2
–1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VDD/VSS = 30V/0V
VLOGIC = 5V
VA = VDD
VB = VSS
VWB, CODE: HALF-SCALE,
NORMAL MODE
VWB, CODE: HALF-SCALE,
R-PERF MODE
20k
50k
100k
20k
50k
100k
VWB
, CODE: FULL SCALE,
R-PERF MODE
Figure 50. 20kΩ Large-Signal Settling Time from Code Zero Scale
8
0
1
2
3
4
5
6
7
0
256
512
768
1023
0
64
128
192
255
AD5292
AD5291
TH
EOR
E
T
IC
A
L
I
WB
_M
A
X
(m
A
)
CODE (Decimal)
07
674-
0
29
VDD/VSS = 30V/0V
VA = VDD
VB = VSS
50k
20k
100k
Figure 51. Theoretical Maximum Current vs. Code
07
67
4-
0
35
1.2
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
VO
L
T
A
G
E
(
V)
TIME (s)
–2
0
2
4
6
8
10
12
14
16
VDD/VSS = ±15V
VLOGIC = +5V
VA = VDD
VB = VSS
50k
20k
100k
Figure 52. Maximum Transition Glitch
40
32
24
40
–32
–24
–16
–8
0
8
16
–0.5
0
5
10
15
20
25
30
35
40
45
VO
L
T
A
G
E
(
μ
V)
TIME (s)
VDD/VSS = ±15V
VA = VDD
VB = VSS
CODE = HALF CODE
07
67
4-
0
32
Figure 53. Digital Feedthrough
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