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參數(shù)資料
| 型號： | EVAL-AD5292EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/32頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5292 |
| 標準包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 嵌入式： | 是 |
| 已用 IC / 零件： | AD5292 |
| 主要屬性： | 1 通道，1024 位置 |
| 次要屬性： | SPI 接口 |
| 已供物品： | 板，CD |
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AD5291/AD5292
Rev. D | Page 25 of 32
RESISTOR PERFORMANCE MODE
This mode activates a new, patented 1% end-to-end resistor
tolerance that ensures a ±1% resistor tolerance on each code,
(AD5291) or Table 5 (AD5292) to check which codes achieve
±1% resistor tolerance. The resistor performance mode is
activated by programming Bit C2 of the control register (see
Table 13 and Table 14). The typical settling time is shown in
RESET
A low-to-high transition of the hardware RESET pin loads the
RDAC register with the contents of the most recently programmed
20-TP memory location. The AD5291 and AD5292 can also be
reset through software by executing Command 4 (see
).
If no 20-TP memory location is programmed, then the RDAC
register loads with midscale upon reset. The control register is
restored with default bits; see
.
SDO PIN AND DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes: it can be
used to read the contents of the wiper setting, 50-TP values and
control register using Command 2, Command 5 and Command 7,
respectively (see Table 11) or the SDO pin can be used in daisy-
chain mode. Data is clocked out of SDO on the rising edge of
SCLK. The SDO pin contains an open-drain N-channel FET
that requires a pull-up resistor if this pin is used. To place the
pin in high impedance and minimize the power dissipation
when the pin is used, the 0x8001 data word followed by
Command 0 should be sent to the part. Table 17 provides a
sample listing for the sequence of the serial data input (DIN).
Daisy chaining minimizes the number of port pins required
from the controlling IC. As shown in Figure 64, users need to
tie the SDO pin of one package to the DIN pin of the next
package. Users may need to increase the clock period, because
the pull-up resistor and the capacitive loading at the SDO-to-
DIN interface may require additional time delay between
subsequent devices.
When two AD5291 and AD5292 devices are daisy-chained, 32
bits of data are required. The first 16 bits go to U2, and the
second 16 bits go to U1. Hold the SYNC pin low until all 32 bits
are clocked into their respective shift registers. The SYNC pin is
then pulled high to complete the operation.
Keep the SYNC pin low until all 32 bits are clocked into their
respective serial registers. The SYNC pin is then pulled high to
complete the operation.
DIN
SDO
SCLK
RP
2.2k
DIN
SDO
U1
U2
AD5291/
AD5292
AD5291/
AD5292
SYNC
VLOGIC
MICRO-
CONTROLLER
SCLK
SS
MOSI
SYNC
07
674
-05
0
Figure 64. Daisy-Chain Configuration Using SDO
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices has patented
the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5291 and AD5292 employ
a three-stage segmentation approach, as shown in Figure 65.
The AD5291 and AD5292 wiper switches are designed with the
transmission gate CMOS topology and with the gate voltages
derived from VDD and VSS.
RW
SW
W
RW
8-/10-BIT
ADDRESS
DECODER
A
RL
RM
B
RM
RL
07
67
4
-05
1
Figure 65. Simplified RDAC Circuit
Table 17. Minimize Power Dissipation at SDO Pin
DIN
Action
0xXXXX
Last user command sent to the digipot
0x8001
0xXXXX
Prepares the SDO pin to be placed in high impedance mode
0x0000
High impedance
The SDO pin is placed in high impedance
1 X is don’t care.
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