RAB = 50 kΩ R
參數(shù)資料
型號： EVAL-AD5292EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 31/32頁
文件大小： 0K
描述： BOARD EVAL FOR AD5292
標準包裝： 1
主要目的： 數(shù)字電位器
嵌入式： 是
已用 IC / 零件： AD5292
主要屬性： 1 通道，1024 位置
次要屬性： SPI 接口
已供物品： 板，CD
AD5291/AD5292
Rev. D | Page 8 of 32
Table 6.
RAB = 50 kΩ
RAB = 100 kΩ
|VDD VSS| = 26 V to 33 V
|VDD VSS| = 21 V to 26 V
|VDD VSS| = 26 V to 33 V
|VDD VSS| = 21 V to 26 V
Resistor
Tolerance per
Code
RWB
RWA
RWB
RWA
RWB
RWA
RWB
RWA
1% R-Tolerance
From 0x08C
to 0x3FF
From 0x000
to 0x35F
From 0x0B4
to 0x3FF
From 0x000
to 0x31E
From 0x04B
to 0x3FF
From 0x000
to 0x3B4
From 0x064
to 0x3FF
From 0x000
to 0x39B
2% R-Tolerance
From 0X03C
to 0x3FF
From 0x000
to 0x3C3
From 0x050
to 0x3FF
From 0x000
to 0x3AF
From 0x028
to 0x3FF
From 0x000
to 0x3D7
From 0x028
to 0x3FF
From 0x000
to 0x3D7
3% R-Tolerance
From 0X028
to 0x3FF
From 0x000
to 0x3D7
From 0x032
to 0x3FF
From 0x000
to 0x3CD
From 0x019
to 0x3FF
From 0x000
to 0x3E6
From 0x019
to 0x3FF
From 0x000
to 0x3E6
INTERFACE TIMING SPECIFICATIONS
VDD/VSS = ±15 V, VLOGIC = 2.7 V to 5.5 V, 40°C < TA < +105°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 7.
Parameter
Unit
Description
20
ns min
SCLK cycle time
t2
10
ns min
SCLK high time
t3
10
ns min
SCLK low time
t4
10
ns min
SYNC to SCLK falling edge setup time
t5
5
ns min
Data setup time
t6
5
ns min
Data hold time
t7
1
ns min
SCLK falling edge to SYNC rising edge
t8
ns min
Minimum SYNC high time
t9
14
ns min
SYNC rising edge to next SCLK fall ignore
1
ns min
RDY rising edge to SYNC falling edge
40
ns max
SYNC rising edge to RDY fall time
2.4
μs max
RDY low time, RDAC register write command execute time (R-Perf mode)
410
ns max
RDY low time, RDAC register write command execute time (normal mode)
8
ms max
RDY low time, memory program execute time
1.5
ms min
Software/hardware reset
450
ns max
RDY low time, RDAC register readback execute time
1.3
ms max
RDY low time, memory readback execute time
450
ns max
SCLK rising edge to SDO valid
tRESET
20
ns min
Minimum RESET pulse width (asynchronous)
tPOWER-UP5
2
ms max
Power-on OTP restore time
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 50 MHz.
3 Refer to t12 and t13 for RDAC register and memory commands operations.
4 RPULL_UP = 2.2 kΩ to VLOGIC, with a capacitance load of 168 pF.
5 Maximum time after VLOGIC is equal to 2.5 V.
DATA BITS
DB9 (MSB)
DB0 (LSB)
D7
D6
D5
D4
D3
D2
D1
D0
CONTROL BITS
C0
C1
C2
D9
D8
C3
0
07
67
4-
00
3
Figure 2. Shift Register Content
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