參數(shù)資料
型號(hào)： EVAL-AD5424EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/29頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD5424
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 1
位數(shù)： 8
采樣率（每秒）： 20.4M
數(shù)據(jù)接口： 并聯(lián)
設(shè)置時(shí)間： 30µs
DAC 型： 電流
工作溫度： -40°C ~ 125°C
已供物品： 板，CD
已用 IC / 零件： AD5424
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Data Sheet
AD5424/AD5433/AD5445
Rev. D | Page 9 of 28
03160-008
9
12
DB6
DB3
10
11
DB5
DB4
1
2
3
4
5
6
7
8
20
13
14
15
16
17
18
19
AD5445
(Not to Scale)
IOUT1
IOUT2
GND
DB11
DB10
DB9
DB8
DB7
RFB
VREF
VDD
R/W
CS
DB0 (LSB)
DB1
DB2
Figure 7. AD5445 Pin Configuration (TSSOP)
03160-
109
14
13
12
1
3
4
CS
15 R/W
DB0
DB1
11 DB2
GND
DB10
2
DB11
DB9
5
DB8
7
DB6
6
DB7
8
DB5
9
DB4
10
DB3
19
I O
UT
1
20
I O
UT
2
18
R
FB
17
V
RE
F
16
V
DD
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
AD5445
TOP VIEW
(Not to Scale)
Figure 8. AD5445 Pin Configuration (LFCSP)
Table 6. AD5445 Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
Description
1
19
IOUT1
DAC Current Output.
2
20
IOUT2
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3
1
GND
Ground Pin.
4 to 15
2 to 13
DB11 to DB0
Parallel Data Bits 11 to 0.
16
14
CS
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input
latch or to read data from the DAC register. Rising edge of CS loads data.
17
15
R/W
Read/Write. When low, use in conjunction with CS to load parallel data. When high, use with
CS to read back contents of DAC register.
18
16
VDD
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
19
17
VREF
DAC Reference Voltage Input Terminal.
20
18
RFB
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external
amplifier output.
Not applicable
EPAD
Exposed Pad. The exposed pad must be connected to AGND.
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