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參數資料
| 型號： | EVAL-AD5443-DBRDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 22/25頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL CARD CLINUX/STAMP |
| 產品培訓模塊： | DAC Architectures |
| 標準包裝： | 1 |
| DAC 的數量： | 1 |
| 位數： | 12 |
| 采樣率（每秒）： | 2.5M |
| 數據接口： | 串行 |
| 設置時間： | 50ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 125°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5443 |
| 產品目錄頁面： | 788 (CN2011-ZH PDF) |
| 相關產品： | AD5443YRMZ-REEL7-ND - IC DAC 12BIT SERIAL IN 10MSOP AD5443YRMZ-REEL-ND - IC DAC 12BIT SERIAL IN 10MSOP AD5443YRMZ-ND - IC DAC 12BIT SERIAL IOUT 10-MSOP AD5443YRM-ND - IC DAC 12BIT SERIAL IOUT 10-MSOP |
Data Sheet
AD5426/AD5432/AD5443
Rev. G | Page 5 of 24
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V; temperature range for Y version: 40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
2.5 V to 5.5 V
4.5 V to 5.5 V
Unit
Test Conditions/Comments
fSCLK
50
MHz max
Max clock frequency
t1
20
ns min
SCLK cycle time
t2
8
ns min
SCLK high time
t3
8
ns min
SCLK low time
13
ns min
SYNC falling edge to SCLK active edge setup time
t5
5
ns min
Data setup time
t6
3
ns min
Data hold time
t7
5
ns min
SYNC rising edge to SCLK active edge
t8
30
ns min
Minimum SYNC high time
80
45
ns typ
SCLK active edge to SDO valid
120
65
ns max
1 Falling or rising edge as determined by control bits of serial word.
2 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with load circuit, as shown in Figure 4.
3 SDO operates with a VDD of 3.0 V to 5.5 V.
DB15
DB0
SCLK
SYNC
DIN
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF
SCLK AS DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED.
t1
t8
t4
t3
t2
t5
t6
t7
03162-002
Figure 2. Standalone Mode Timing Diagram
DB15 (N)
DB0 (N)
DB15
(N + 1)
DB0
(N + 1)
SCLK
SDIN
SDO
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED.
t6
DB15(N)
DB0(N)
t1
t2
t5
t9
t6
t4
t3
t7
t8
SYNC
03162-003
Figure 3. Daisy-Chain and Readback Modes Timing Diagram
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相關代理商/技術參數 |
參數描述 |
|---|---|
| EVAL-AD5443EB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD5443, 0BIT HIGH BANDWIDTH MULTIPLYING DACS W/ - Bulk |
| EVAL-AD5443EBZ | 功能描述:BOARD EVAL FOR AD5433 RoHS:是 類別:編程器，開發(fā)系統 >> 評估板 - 數模轉換器 (DAC) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數量:4 位數:12 采樣率（每秒）:- 數據接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5443SDZ | 功能描述:BOARD EVAL FOR AD5443 RoHS:是 類別:編程器，開發(fā)系統 >> 評估板 - 數模轉換器 (DAC) 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數量:4 位數:12 采樣率（每秒）:- 數據接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD5444EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD5444EBZ | 制造商:Analog Devices 功能描述:EVAL KIT FOR 12-/14BIT HIGH BANDWIDTH MULTIPLYING DACS W/ SE - Bulk |
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