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參數(shù)資料
型號(hào)： EVAL-AD5443-DBRDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/25頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL CARD CLINUX/STAMP
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 2.5M
數(shù)據(jù)接口： 串行
設(shè)置時(shí)間： 50ns
DAC 型： 電流
工作溫度： -40°C ~ 125°C
已供物品： 板，CD
已用 IC / 零件： AD5443
產(chǎn)品目錄頁(yè)面： 788 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD5443YRMZ-REEL7-ND - IC DAC 12BIT SERIAL IN 10MSOP
AD5443YRMZ-REEL-ND - IC DAC 12BIT SERIAL IN 10MSOP
AD5443YRMZ-ND - IC DAC 12BIT SERIAL IOUT 10-MSOP
AD5443YRM-ND - IC DAC 12BIT SERIAL IOUT 10-MSOP
Data Sheet
AD5426/AD5432/AD5443
Rev. G | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IOUT1 1
IOUT2 2
GND
3
SCLK
4
SDIN
5
RFB
10
VREF
9
VDD
8
SDO
7
SYNC
6
AD5426/
AD5432/
AD5443
TOP VIEW
(Not to Scale)
03162-005
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
IOUT1
DAC Current Output.
2
IOUT2
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3
GND
Digital Ground Pin.
4
SCLK
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device may be configured such that data is clocked into
the shift register on the rising edge of SCLK. The device can accommodate clock rates up to 50 MHz.
5
SDIN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the
user to change the active edge to rising edge.
6
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the mode, the serial
interface counts clocks, and data is latched to the shift register on the 16th active clock edge.
7
SDO
Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes
the DAC register contents available for readback on the SDO pin, clocked out on the opposite edges to the active
clock edge. SDO operates with a VDD of 3.0 V to 5.5 V.
8
VDD
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
9
VREF
DAC Reference Voltage Input.
10
RFB
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
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