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參數(shù)資料
型號： EVAL-AD5755SDZ
廠商： Analog Devices Inc
文件頁數(shù)： 42/52頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5755
視頻文件： AD5755: 16-Bit Multi-Channel, Voltage and Current Output DAC
標準包裝： 1
DAC 的數(shù)量： 4
位數(shù)： 16
數(shù)據(jù)接口： 串行
設置時間： 11µs
DAC 型： 電流/電壓
工作溫度： -40°C ~ 105°C
已供物品： 板
已用 IC / 零件： AD5755
Data Sheet
AD5755
Rev. C | Page 47 of 52
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads, a capacitor
may be required between IOUT_x and AGND to ensure stability.
A 0.01 F capacitor between IOUT_x and AGND ensures stability
of a load of 50 mH. The capacitive component of the load may
cause slower settling, although this may be masked by the set-
tling time of the AD5755. There is no maximum capacitance
limit for the current output of the AD5755.
TRANSIENT VOLTAGE PROTECTION
The AD5755 contains ESD protection diodes that prevent dam-
age from normal handling. The industrial control environment
can, however, subject I/O circuits to much higher transients. To
protect the AD5755 from excessively high voltage transients,
external power diodes and a surge current limiting resistor (RP)
are required, as shown in Figure 84. A typical value for RP is 10 .
The two protection diodes and the resistor (RP) must have appro-
priate power ratings.
RLOAD
R
D2
D1
P
AD5755
VBOOST_x
IOUT_x
AGND
AVSS
CDCDC
4.7F
CFILTER
0.1F
RFILTER
10
(FROM
DC-TO-DC
CONVERTER)
07304-
279
Figure 84. Output Transient Voltage Protection
Further protection can be provided using transient voltage
suppressors (TVSs), also referred to as transorbs. These compo-
nents are available as unidirectional suppressors, which protect
against positive high voltage transients, and as bidirectional
suppressors, which protect against both positive and negative
high voltage transients. Transient voltage suppressors are avail-
able in a wide range of standoff and breakdown voltage ratings.
The TVS should be sized with the lowest breakdown voltage
possible while not conducting in the functional range of the
current output.
It is recommended that all field connected nodes be protected.
The voltage output node can be protected with a similar circuit,
where D2 and the transorb are connected to AVSS. For the volt-
age output node, the +VSENSE_x pin should also be protected with
a large value series resistance to the transorb, such as 5 k. In
this way, the IOUT_x and VOUT_x pins can also be tied together and
share the same protection circuitry.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5755 is via a serial bus that
uses a protocol compatible with microcontrollers and DSP
processors. The communications channel is a 3-wire minimum
interface consisting of a clock signal, a data signal, and a latch
signal. The AD5755 requires a 24-bit data-word with data valid
on the falling edge of SCLK.
The DAC output update is initiated on either the rising edge of
LDAC or, if LDAC is held low, on the rising edge of SYNC. The
contents of the registers can be read using the readback function.
AD5755-TO-ADSP-BF527 INTERFACE
The AD5755 can be connected directly to the SPORT interface
of the ADSP-BF527, an Analog Devices, Inc., Blackfin DSP.
Figure 85 shows how the SPORT interface can be connected to
control the AD5755.
07304-
080
AD5755
SYNC
SCLK
SDIN
LDAC
SPORT_TFS
SPORT_TSCK
SPORT_DTO
GPIO0
ADSP-BF527
Figure 85. AD5755-to-ADSP-BF527 SPORT Interface
LAYOUT GUIDELINES
Layout—Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5755 is mounted should be designed so that the analog and
digital sections are separated and confined to certain areas of the
board. If the AD5755 is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only. The star ground point should be
established as close as possible to the device.
The GNDSWx and ground connection for the AVCC supply are
referred to as PGND. PGND should be confined to certain areas
of the board, and the PGND-to-AGND connection should be
made at one point only.
Layout—Supply Decoupling
The AD5755 should have ample supply bypassing of 10 F
in parallel with 0.1 F on each supply located as close to the
package as possible, ideally right up against the device. The
10 F capacitors are the tantalum bead type. The 0.1 F
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESL), such as the common
ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching.
Layout—Traces
The power supply lines of the AD5755 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground to
prevent radiating noise to other parts of the board and should
never be run near the reference inputs. A ground line routed
between the SDIN and SCLK lines helps reduce crosstalk
between them (not required on a multilayer board that has a
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