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參數(shù)資料
型號： EVAL-AD5755SDZ
廠商： Analog Devices Inc
文件頁數(shù)： 7/52頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5755
視頻文件： AD5755: 16-Bit Multi-Channel, Voltage and Current Output DAC
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 4
位數(shù)： 16
數(shù)據(jù)接口： 串行
設(shè)置時間： 11µs
DAC 型： 電流/電壓
工作溫度： -40°C ~ 105°C
已供物品： 板
已用 IC / 零件： AD5755
Data Sheet
AD5755
Rev. C | Page 15 of 52
Pin No.
Mnemonic
Description
44
SWC
Switching Output for Channel C DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown
45
AVCC
Supply for DC-to-DC Circuitry.
46
VBOOST_C
Supply for Channel C Current Output Stage (see Figure 72). This is also the supply for the VOUT_x stage, which is
regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in
47
IOUT_C
Current Output Pin for DAC Channel C.
48
COMPDCDC_C
DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of the Channel C dc-to-dc converter. Alternatively, if using an external compensation resistor,
place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation
information).
49
VOUT_C
Buffered Analog Output Voltage for DAC Channel C.
50
+VSENSE_C
Sense Connection for the Positive Voltage Output Load Connection for VOUT_C.
51
VSENSE_C
Sense Connection for the Negative Voltage Output Load Connection for VOUT_C. This pin must stay within ±3.0 V
of AGND for specified operation.
52
COMPLV_C
Optional Compensation Capacitor Connection for VOUT_C Output Buffer. Connecting a 220 pF capacitor between
this pin and the VOUT_C pin allows the voltage output to drive up to 2 F. Note that the addition of this capacitor
reduces the bandwidth of the output amplifier, increasing the settling time.
53
AVSS
Negative Analog Supply Pin.
54
IOUT_D
Current Output Pin for DAC Channel D.
55
VOUT_D
Buffered Analog Output Voltage for DAC Channel D.
56
VBOOST_D
Supply for Channel D Current Output Stage (see Figure 72). This is also the supply for the VOUT_x stage, which is
regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in
57
COMPDCDC_D
DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of Channel D dc-to-dc converter. Alternatively, if using an external compensation resistor, place a
resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors
and AICC Supply Requirements—Slewing sections in the Device Features section for more information).
58
+VSENSE_D
Sense Connection for the Positive Voltage Output Load Connection for VOUT_D.
59
VSENSE_D
Sense Connection for the Negative Voltage Output Load Connection for VOUT_D. This pin must stay within ±3.0 V
of AGND for specified operation.
60
COMPLV_D
Optional Compensation Capacitor Connection for VOUT_D Output Buffer. Connecting a 220 pF capacitor between
this pin and the VOUT_D pin allows the voltage output to drive up to 2 F. Note that the addition of this capacitor
reduces the bandwidth of the output amplifier, increasing the settling time.
61
REFIN
External Reference Voltage Input.
62
REFOUT
Internal Reference Voltage Output. It is recommended to place a 0.1 F capacitor between REFOUT and
REFGND.
63
RSET_D
An external, precision, low drift 15 k current setting resistor can be connected to this pin to improve the IOUT_D
temperature drift performance. See the Device Features section.
64
RSET_C
An external, precision, low drift 15 k current setting resistor can be connected to this pin to improve the IOUT_C
temperature drift performance. See the Device Features section.
EPAD
Exposed Pad. This exposed pad should be connected to the potential of the AVSS pin, or, alternatively, it can be
left electrically unconnected. It is recommended that the pad be thermally connected to a copper plane for
enhanced thermal performance.
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