Isolated Sigma-Delta Modulator
AD7401
Rev. D
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FEATURES
20 MHz maximum external clock rate
Second-order modulator
16 bits no missing codes
±2 LSB INL typical at 16 bits
3.5 μV/°C maximum offset drift
On-board digital isolator
On-board reference
Low power operation: 20 mA maximum at 5.25 V
40°C to +105°C operating range
16-lead SOIC package
Safety and regulatory approvals
UL recognition
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 891 V peak
APPLICATIONS
AC motor controls
Data acquisition systems
A/D + opto-isolator replacements
GENERAL DESCRIPTION
The AD7401
1 is a second-order, sigma-delta (Σ-Δ) modulator
that converts an analog input signal into a high speed, 1-bit data
stream with on-chip digital isolation based on Analog Devices,
Inc. iCoupler technology. The AD7401 operates from a 5 V
power supply and accepts a differential input signal of ±200 mV
(±320 mV full scale). The analog input is continuously sampled
by the analog modulator, eliminating the need for external
sample-and-hold circuitry. The input information is contained
in the output stream as a density of ones with a data rate up to
20 MHz. The original information can be reconstructed with an
appropriate digital filter. The serial I/O can use a 5 V or a 3 V
supply (VDD2).
The serial interface is digitally isolated. High speed CMOS,
combined with monolithic air core transformer technology,
means the on-chip isolation provides outstanding performance
characteristics, superior to alternatives such as optocoupler
devices. The part contains an on-chip reference. The AD7401
is offered in a 16-lead SOIC and has an operating temperature
range of 40°C to +105°C.
An internal clock version,
AD7400, is also available.
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.
FUNCTIONAL BLOCK DIAGRAM
VIN+
VDD1
VDD2
VIN–
Σ- ADC
CONTROL LOGIC
AD7401
BUF
T/H
REF
WATCHDOG
GND1
GND2
MDAT
MCLKIN
DECODE
ENCODE
DECODE
ENCODE
UPDATE
WATCHDOG
UPDATE
05
85
1-
0
01
Figure 1.