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參數(shù)資料
| 型號(hào)： | EVAL-AD7401EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7401 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | iCoupler® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±320 mV |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 100mW @ 20MSPS |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7401 |
| 已供物品： | 板 |
AD7401
Rev. D | Page 16 of 20
always @ (posedge word_clk or posedge reset)
if(reset)
begin
acc3_d2 <= 0;
diff1_d <= 0;
diff2_d <= 0;
diff1 <= 0;
diff2 <= 0;
diff3 <= 0;
end
else
begin
diff1 <= acc3 - acc3_d2;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d2 <= acc3;
diff1_d <= diff1;
diff2_d <= diff2;
end
/* Clock the Sinc output into an output
register
WORD_CLK
DATA
DIFF3
05
851
-02
6
Figure 28. Clocking Sinc Output into an Output Register
WORD_CLK = output word rate
*/
always @ (posedge word_clk)
begin
DATA[15] <= diff3[23];
DATA[14] <= diff3[22];
DATA[13] <= diff3[21];
DATA[12] <= diff3[20];
DATA[11] <= diff3[19];
DATA[10] <= diff3[18];
DATA[9]
<= diff3[17];
DATA[8]
<= diff3[16];
DATA[7]
<= diff3[15];
DATA[6]
<= diff3[14];
DATA[5]
<= diff3[13];
DATA[4]
<= diff3[12];
DATA[3]
<= diff3[11];
DATA[2]
<= diff3[10];
DATA[1]
<= diff3[9];
DATA[0]
<= diff3[8];
end
endmodule
80
70
60
50
40
30
20
10
0
90
10
100
1k
1
DECIMATION RATE
S
NR
(
d
B)
SINC3
SINC2
SINC1
05
85
1-
03
5
Figure 29. SNR vs. Decimation Rate for Different Filter Types
Figure 29 shows a plot of SNR performance vs. decimation rate
with different filter types. Note that, for a given bandwidth
requirement, a higher MCLKIN frequency can allow higher
decimation rates to be used, resulting in higher SNR performance.
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