Y Version1, 2 Unit Test Conditions/Comments LOGIC OUTPUTS
參數(shù)資料
型號: EVAL-AD7401EDZ
廠商: Analog Devices Inc
文件頁數(shù): 15/20頁
文件大小: 0K
描述: BOARD EVALUATION FOR AD7401
標(biāo)準(zhǔn)包裝: 1
系列: iCoupler®
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 20M
數(shù)據(jù)接口: 串行
輸入范圍: ±320 mV
在以下條件下的電源(標(biāo)準(zhǔn)): 100mW @ 20MSPS
工作溫度: -40°C ~ 105°C
已用 IC / 零件: AD7401
已供物品:
AD7401
Rev. D | Page 4 of 20
Parameter
Y Version1, 2
Unit
Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, VOH
VDD2 0.1
V min
IO = 200 μA
Output Low Voltage, VOL
0.4
V max
IO = +200 μA
POWER REQUIREMENTS
VDD1
4.5/5.25
V min/V max
VDD2
3/5.5
V min/V max
IDD16
mA max
VDD1 = 5.25 V
IDD27
8
mA max
VDD2 = 5.5 V
4
mA max
VDD2 = 3.3 V
1 Temperature range is 40°C to +85°C.
2 All voltages are relative to their respective ground.
4 For fMCLK > 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, VDD1 = VDD2 = 5 V ± 5%, and TA = 40°C to +85°C.
5 Sample tested during initial release to ensure compliance.
TIMING SPECIFICATIONS
VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, TA = TMAX to TMIN, unless otherwise noted.1
Table 2.
Parameter
Limit at TMIN, TMAX
Unit
Description
20
MHz max
Master clock input frequency
5
MHz min
Master clock input frequency
25
ns max
Data access time after MCLK rising edge
15
ns min
Data hold time after MCLK rising edge
t3
0.4 × tMCLKIN
ns min
Master clock low time
t4
0.4 × tMCLKIN
ns min
Master clock high time
1 Sample tested during initial release to ensure compliance
2 Mark space ratio for clock input is 40/60 to 60/40 for fMCLKIN to 16 MHz and 48/52 to 52/48 for fMCLKIN > 16 MHz to 20 MHz.
3 VDD1 = VDD2 = 5 V
± 5% for fMCLKIN > 16 MHz to 20 MHz.
4 Measured with the load circuit of
and defined as the time required for the output to cross 0.8 V or 2.0 V.
200A
IOL
200A
IOH
1.6V
TO OUTPUT
PIN
CL
25pF
05
85
1-
00
2
Figure 2. Load Circuit for Digital Output Timing Specifications
MCLKIN
MDAT
t1
t2
t4
t3
05
85
1-
0
03
Figure 3. Data Timing
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