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參數(shù)資料
| 型號(hào)： | EVAL-AD7693CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7693 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 18mW @ 500kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7693 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD7693BRMZRL7-ND - IC ADC 16BIT 500KSPS 10-MSOP AD7693BCPZRL7TR-ND - IC ADC 16BIT 500KSPS 10-LFCSP AD7693BRMZ-ND - IC ADC 16BIT 500KSPS 10-MSOP AD7693BCPZRL-ND - IC ADC 16BIT 500KSPS 10LFCSP |
AD7693
Rev. A | Page 20 of 24
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host with an interrupt input and it
is desired to keep CNV, which is used to sample the analog
input, independent of the signal used to select the data reading.
This requirement is particularly important in applications
where low jitter on CNV is desired.
The connection diagram is shown in Figure 40, and the
corresponding timing is given in Figure 41.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7693
then enters the acquisition phase and powers down. The data
bits are clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge will allow a faster reading rate, provided it has an
acceptable hold time. After the optional 17th SCK falling edge,
or when SDI goes high (whichever occurs first), SDO returns to
high impedance.
DATA IN
IRQ
CLK
CONVERT
CS1
VIO
CNV
SCK
SDO
SDI
AD7693
06
39
4-
03
9
DIGITAL HOST
Figure 40. CS Mode, 4-Wire with Busy Indicator Connection Diagram
SDO
D15
D14
D1
D0
tDIS
SCK
1
2
3
15
16
17
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV
06
39
4-
0
40
Figure 41. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7693SDZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 EVAL BOARD 16-bit ADC 500kSPS RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| EVAL-AD7694CB | 制造商:Analog Devices 功能描述: |
| EVAL-AD7694CB1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 250 kSPS PulSAR ADC in MSOP |
| EVAL-AD7694CBZ | 功能描述:BOARD EVALUATION FOR AD7694 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:PulSAR® 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7694SDZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 EVALUATION BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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