參數(shù)資料
型號: EVAL-AD7693CBZ
廠商: Analog Devices Inc
文件頁數(shù): 9/24頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD7693
標(biāo)準(zhǔn)包裝: 1
系列: PulSAR®
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 500k
數(shù)據(jù)接口: 串行
輸入范圍: ±VREF
在以下條件下的電源(標(biāo)準(zhǔn)): 18mW @ 500kSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD7693
已供物品:
相關(guān)產(chǎn)品: AD7693BRMZRL7-ND - IC ADC 16BIT 500KSPS 10-MSOP
AD7693BCPZRL7TR-ND - IC ADC 16BIT 500KSPS 10-LFCSP
AD7693BRMZ-ND - IC ADC 16BIT 500KSPS 10-MSOP
AD7693BCPZRL-ND - IC ADC 16BIT 500KSPS 10LFCSP
AD7693
Rev. A | Page 17 of 24
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 34, and the corresponding timing is given in
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This could be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers; however, CNV must be
returned high before the minimum conversion time elapses and
then held high for the maximum possible conversion time to
avoid the generation of the busy signal indicator. When the
conversion is complete, the AD7693 enters the acquisition
phase and powers down. When CNV goes low, the MSB is
output onto SDO. The remaining data bits are clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16th SCK falling edge or when CNV goes high (whichever
occurs first), SDO returns to high impedance.
CNV
SCK
SDO
SDI
DATA IN
CLK
CONVERT
VIO
AD7693
06
39
4-
03
3
DIGITAL HOST
Figure 34. CS Mode, 3-Wire Without Busy Indicator
Connection Diagram (SDI High)
SDO
D15
D14
D13
D1
D0
tDIS
SCK
123
14
15
16
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
tEN
06
39
4-
0
34
Figure 35. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
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