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參數(shù)資料
| 型號： | EVAL-AD7739EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/32頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7739 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 15.1k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±2.5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 85mW @ 5V |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7739 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD7739BRUZ-REEL7-ND - IC ADC 24BIT 8CH SIG-DEL 24TSSOP AD7739BRUZ-ND - IC ADC 24BIT 8-CH 24-TSSOP AD7739BRU-REEL-ND - IC ADC 24BIT 8CH SIG-DEL 24TSSOP AD7739BRU-ND - IC ADC 24BIT 8-CH 24-TSSOP |
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AD7739
Data Sheet
Rev. A | Page 20 of 32
Bit
Mnemonic
Description
4
CLKDIS
Master clock output disable. When this bit is set to 1, the master clock is disabled from appearing at the
MCLKOUT pin and the MCLKOUT pin is in a high impedance state. This allows turning off the MCLKOUT as a
power saving feature. When using an external clock on MCLKIN, the AD7739 continues to have internal clocks
and converts normally regardless of the CLKDIS bit state. When using a crystal oscillator or ceramic resonator
across the MCLKIN and MCLKOUT pins, the AD7739 clock is stopped and no conversions can take place when the
CLKDIS bit is active. The AD7739 digital interface can still be accessed using the SCLK pin.
3
Dump
Dump mode. When this bit is reset to 0, the channel status register and channel data register are addressed and
read separately. When the dump bit is set to 1, the channel status register is followed immediately by a read of
the channel data register regardless of whether the status or data register has been addressed through the
communications register. The continuous read mode is always dump mode reading the channel status and
channel data registers, regardless of the dump bit value (see the Digital Interface Description section for details).
2
Cont RD
When this bit is set to 1, the AD7739 operates in the continuous read mode (see the Digital Interface Description
section for details).
1
24/16 bit
Channel data register data width selection bit. When set to 1, the channel data registers are 24 bits wide. When
set to 0, the channel data registers is 16 bits wide.
0
Clamp
This bit determines the value of the channel data register when the analog input voltage is outside the nominal
input voltage range. When the clamp bit is set to 1, the channel data register is digitally clamped to either all 0s
or all 1s when the analog input voltage goes outside the nominal input voltage range. When the clamp bit is
reset to 0, the data registers reflect the analog input voltage even outside the nominal voltage range (see the
Table 29. Mode Settings
MD2 MD1 MD0 Operating Mode Description
0
Idle
The default mode after power-on or reset. The AD7739 automatically returns to this mode after any
calibration or after a single conversion.
0
1
Continuous
conversion
The AD7739 performs a conversion on the specified channel. After the conversion is complete, the
relevant channel data register and channel status register are updated, the relevant RDY bit in the
ADC status register is set, and the AD7739 continues converting on the next enabled channel. The
part cycles through all enabled channels until it is put into another mode or reset. The cycle period is
the sum of all enabled channels’ conversion times, set by the corresponding channel conversion time
registers.
0
1
0
Single
conversion
The AD7739 performs a conversion on the specified channel. After the conversion is complete, the
relevant channel data register and channel status register are updated, the relevant RDY bit in the
ADC status register is set, the RDY pin goes low, the MD2 to MD0 bits are reset, and the AD7739
returns to idle mode. Requesting a single conversion ignores the channel setup register enable bits; a
conversion is performed even if that channel is disabled.
0
1
Power-down
(standby)
The ADC and the analog front end (internal buffer) go into the power-down mode. The AD7739
digital interface can still be accessed. The CLKDIS bit works separately, and the MCLKOUT mode is not
affected by the power-down (standby) mode.
1
0
ADC zero-scale
self-calibration
A zero-scale self-calibration is performed on internally shorted ADC inputs. After the calibration is
complete, the contents of the ADC zero-scale calibration register are updated, all RDY bits in the ADC
status register are set, the RDY pin goes low, the MD2 to MD0 bits are reset, and the AD7739 returns
to idle mode.
1
0
1
ADC full-scale
self-calibration
A full-scale self-calibration is performed on an internally generated full-scale signal. After the
calibration is complete, the contents of the ADC full-scale calibration register are updated, all RDY bits
in the ADC status register are set, the RDY pin goes low, the MD2 to MD0 bits are reset, and the
AD7739 returns to idle mode.
1
0
Channel zero-
scale system
calibration
A zero-scale system calibration is performed on the selected channel. An external system zero-scale
voltage must be provided at the AD7739 analog input and this voltage must remain stable for the
duration of the calibration. After the calibration is complete, the contents of the corresponding
channel zero-scale calibration register are updated, all RDY bits in the ADC status register are set,
the RDY pin goes low, the MD2 to MD0 bits are reset, and the AD7739 returns to idle mode.
1
Channel full-
scale system
calibration
A full-scale system calibration is performed on the selected channel. An external system full-scale
voltage must be provided at the AD7739 analog input and this voltage must remain stable for the
duration of the calibration. After the calibration is complete, the contents of the corresponding
channel full-scale calibration register are updated, all RDY bits in the ADC status register are set,
the RDY pin goes low, the MD2 to MD0 bits are reset, and the AD7739 returns to idle mode.
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