AD7739
Data Sheet
Rev. A | Page 6 of 32
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
WRITE OPERATION
t11
0
ns
CS falling edge to SCLK falling edge setup
t12
30
ns
Data valid to SCLK rising edge setup time
t13
25
ns
Data valid after SCLK rising edge hold time
t14
50
ns
SCLK high pulse width
t15
50
ns
SCLK low pulse width
t16
0
ns
CS rising edge after SCLK rising edge hold time
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of
2 These numbers are measured with the load circuit of Figure 4 and defined as the time required for the output to cross the VOL or VOH limits. 3 This specification is relevant only if CS goes low while SCLK is low.
4 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Specifications are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
TIMING DIAGRAMS
Figure 2. Read Cycle Timing Diagram
Figure 3. Write Cycle Timing Diagram
Figure 4. Load Circuit for Access Time and Bus Relinquish Time
DOUT
MSB
LSB
CS
t4
t5A
t5
t6
t7
t9
t8
SCLK
03742-0-002
DIN
MSB
LSB
SCLK
CS
t11
t14
t15
t16
t13
t12
03742-0-003
ISOURCE (200A AT DVDD = 5V
100
A AT DV
DD = 3V)
ISINK (800A AT DVDD = 5V
100
A AT DV
DD = 3V)
1.6V
TO OUTPUT
PIN
50pF
03742-0-004