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參數(shù)資料
| 型號： | EVAL-AD7739EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7739 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 15.1k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±2.5 V |
| 在以下條件下的電源（標準）： | 85mW @ 5V |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7739 |
| 已供物品： | 板 |
| 相關產品： | AD7739BRUZ-REEL7-ND - IC ADC 24BIT 8CH SIG-DEL 24TSSOP AD7739BRUZ-ND - IC ADC 24BIT 8-CH 24-TSSOP AD7739BRU-REEL-ND - IC ADC 24BIT 8CH SIG-DEL 24TSSOP AD7739BRU-ND - IC ADC 24BIT 8-CH 24-TSSOP |
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Data Sheet
AD7739
Rev. A | Page 25 of 32
CIRCUIT DESCRIPTION
The AD7739 is a high precision analog-to-digital converter that
is intended for the measurement of wide dynamic range, low
frequency signals in industrial process control, instrumentation,
and PLC systems.
It contains a multiplexer, an input buffer, a Σ-Δ (or charge
balancing) ADC, a digital filter, a clock oscillator, a digital
I/O port, and a serial communications interface.
ANALOG INPUTS
The AD7739 has nine analog input pins connected to the ADC
through the internal multiplexer. The analog front end can be
configured as eight single-ended inputs or four differential
inputs or any combination of these (via the channel setup
registers).
The AD7739 contains a wide bandwidth, fast settling time
differential input buffer capable of driving the dynamic load of
a high speed Σ-Δ modulator. With the internal buffer enabled,
the analog inputs feature high input impedance.
If chopping is enabled or when switching between channels,
there is a dynamic current on analog inputs charging the
internal capacitance of the multiplexer and input buffer. The
capacitance is approximately 10 pF.
At the start of each conversion, there is a delay to allow the
capacitance to be charged (see the Multiplexer, Conversion, and
Data Output Timing section). If the analog inputs resistive
source impedance does not exceed 50 kΩ, the internal
capacitance is charged fast enough and the AD7739
performance is not affected at the 16-bit level.
An external RC filter connected to the analog inputs averages
the multiplexer channel-to-channel switching dynamic currents
to a dc current leading to a dc voltage drop across the external
input resistance. To avoid additional gain errors, offset errors,
and channel-to-channel crosstalk due to this effect, use low
resistor values in the low-pass RC filter for the AD7739. The
recommended low-pass RC filter for the analog inputs is 100 Ω
and 100 nF.
The average (dc) current, charging the capacitance on the
multiplexer output, is related to the equation:
I ≈ CMUX × VMUX × fS
where:
CMUX is the capacitance on the multiplexer output,
approximately 10 pF.
VMUX is the voltage difference on the multiplexer output
between two subsequent conversions, which can be up to 5 V.
fS is the channel sampling frequency, which relates to the sum of
conversion times on all subsequently sampled channels.
SIGMA-DELTA ADC
The AD7739 core consists of a charge balancing Σ-Δ modulator
and a digital filter. The architecture is optimized for fast, fully
settled conversion. This allows for fast channel-to-channel
switching while maintaining inherently excellent linearity, high
resolution, and low noise.
CHOPPING
With chopping enabled, the multiplexer repeatedly reverses the
ADC inputs. Every output data result is then calculated as an
average of two conversions, the first with the positive and the
second with the negative offset term included. This effectively
removes any offset error of the input buffer and Σ-Δ modulator.
Figure 22 shows the channel signal chain with chopping enabled.
Figure 22. Channel Signal Chain Diagram with Chopping Enabled
MULTIPLEXER
+
DIGITAL
FILTER
Σ-
MODULATOR
BUFFER
–
SCALING
ARITHMETIC
(CALIBRATIONS)
CHOP
fMCLK/2
DIGITAL
INTERFACE
OUTPUT DATA
AT THE SELECTED
DATA RATE
AIN(+)
AIN(–)
03742-0-023
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