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| 型號： | EVAL-AD7747EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7747 |
| 標準包裝： | 1 |
| 傳感器類型： | 觸摸，電容式 |
| 接口： | I²C |
| 電源電壓： | 2.7 V ~ 5.25 V |
| 嵌入式： | 否 |
| 已供物品： | 板，纜線，CD |
| 已用 IC / 零件： | AD7747 |
| 產(chǎn)品目錄頁面： | 781 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD7747ARUZ-REEL7-ND - IC CONV CAP TO DIG 24BIT 16TSSOP AD7747ARUZ-REEL-ND - IC CONV CAP TO DIG 24BIT 16TSSOP AD7747ARUZ-ND - IC CONV 24BIT CAP-DGTL 16-TSSOP |
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AD7747
Rev. 0 | Page 21 of 28
CIRCUIT DESCRIPTION
VIN(+)
VDD
CIN1(+)
VIN(–)
SHLD
GND
SDA
SCL
RDY
CIN1(–)
REFIN(+)
REFIN(–)
TEMP
SENSOR
24-BIT Σ-Δ
GENERATOR
DIGITAL
FILTER
I2C
SERIAL
INTERFACE
EXCITATION
CONTROL LOGIC
CALIBRATION
VOLTAGE
REFERENCE
CAP DAC 1
CAP DAC 2
CLOCK
GENERATOR
MUX
AD7747
054
69-
013
Figure 24. AD7747 Block Diagram
OVERVIEW
The AD7747 core is a high precision converter consisting of a
second-order (Σ-Δ or charge balancing) modulator and a third-
order digital filter. It works as a CDC for the capacitive inputs
and as a classic ADC for the voltage input or for the voltage
from a temperature sensor.
In addition to the converter, the AD7747 integrates a multi-
plexer, an excitation source and CAPDACs for the capacitive
inputs, a temperature sensor and a voltage reference for the
voltage and temperature inputs, a complete clock generator,
a control and calibration logic, and an I2C-compatible serial
interface.
CAPACITANCE-TO-DIGITAL CONVERTER
Figure 25 shows the CDC simplified functional diagram. The
measured capacitance CX is connected between the Σ-Δ modu-
lator input and ground. A square-wave excitation signal is
applied on the CX during the conversion and the modulator
continuously samples the charge going through the CX. The
digital filter processes the modulator output, which is a stream
of 0s and 1s containing the information in 0 and 1 density. The
data from the digital filter is scaled, applying the calibration
coefficients, and the final result can be read through the serial
interface.
DIGITAL
FILTER
24-BIT Σ-Δ
MODULATOR
CLOCK
GENERATOR
CAPACITANCE TO DIGITAL CONVERTER
(CDC)
05
46
9-
01
4
EXCITATION
DATA
SHLD
CIN
CX
Figure 25. CDC Simplified Block Diagram
ACTIVE AC SHIELD CONCEPT
The AD7747 measures capacitance between CIN and ground.
That means any capacitance to ground on signal path between
the AD7747 CIN pin(s) and sensor is included in the AD7747
conversion result.
The parasitic capacitance of the sensor connections can easily
be in the same, if not even higher, order as the capacitance of
the sensor itself. If that parasitic capacitance is stable, it can be
treated as a nonchanging capacitive offset. However, the para-
sitic capacitance of sensor connections is often changing as a
result of mechanical movement, changing ambient temperature,
ambient humidity, etc. These changes are seen as drift in the
conversion result and may significantly compromise the system
accuracy.
To eliminate the CIN parasitic capacitance to ground, the
AD7747 SHLD signal can be used for shielding the connection
between the sensor and CIN, as shown in Figure 25. The SHLD
output is basically the same signal waveform as the excitation of
the CIN pin; the SHLD is driven to the same voltage potential
as the CIN pin. Therefore, there is no ac current between CIN
and SHLD pins, and any capacitance between these pins does
not affect the CIN charge transfer. Ideally, the CIN to SHLD
capacitance does not have any contribution to the AD7747 result.
To get the best result, locate the AD7747 as close as possible to
the capacitive sensor. Keep the connection between the sensor
and AD7747 CIN pin, and also the return path between sensor
ground and the AD7747 GND pin, short. Shield the PCB track
to the CIN pin and connect the shielding to the AD7747 SHLD
pin. In addition, if a shielded cable is used for sensor connection,
the shield should be connected to the AD7747 SHLD pin.
CAPDAC
The AD7747 CDC full-scale input range is ±8.192 pF. For sim-
plicity of calculation, however, the following text and figures use
±8 pF. The part can accept a higher capacitance on the input
and the common-mode or offset (nonchanging component)
capacitance can be balanced by programmable on-chip CAPDACs.
DATA
CDC
SHLD
CIN(+)
CIN(–)
CX
CY
CAPDAC(+)
CAPDAC(–)
05
64
9-
0
15
Figure 26. Using a CAPDAC
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