參數(shù)資料
型號: EVAL-AD7747EBZ
廠商: Analog Devices Inc
文件頁數(shù): 27/28頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD7747
標準包裝: 1
傳感器類型: 觸摸,電容式
接口: I²C
電源電壓: 2.7 V ~ 5.25 V
嵌入式:
已供物品: 板,纜線,CD
已用 IC / 零件: AD7747
產(chǎn)品目錄頁面: 781 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: AD7747ARUZ-REEL7-ND - IC CONV CAP TO DIG 24BIT 16TSSOP
AD7747ARUZ-REEL-ND - IC CONV CAP TO DIG 24BIT 16TSSOP
AD7747ARUZ-ND - IC CONV 24BIT CAP-DGTL 16-TSSOP
AD7747
Rev. 0 | Page 8 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
80
–80
–8 –7 –6 –5 –4 –3
–1
–2
8
0
546
9-
0
04
INPUT CAPACITANCE (pF)
IN
L
(
p
m
)
60
40
20
0
–20
–40
–60
01
23
456
7
Figure 4. Capacitance Input Integral Nonlinearity;
VDD = 5 V, CAPDAC = 0x3F
2000
–3000
–50
150
0
546
9-
0
05
TEMPERATURE (C)
G
A
IN
E
R
RO
R
(p
p
m
)
1000
0
–1000
–2000
–25
0
25
50
75
100
125
GAIN TC ≈ –28ppm/C
Figure 5. Capacitance Input Gain Drift vs. Temperature;
VDD = 5 V, CIN(+) to GND = 8 pF
.20
–0.30
–50
150
0
546
9-
0
06
TEMPERATURE (C)
O
F
SET
ER
R
O
R
(f
F
)
–25
0
25
50
75
100
125
.15
.10
.050
–0.05
–0.10
–0.15
–0.20
–0.25
Figure 6. Capacitance Input Offset Drift vs. Temperature;
VDD = 5 V, CIN(+) Open
10
–50
0
600
500
0
546
9-
0
07
CAPACITANCE SHLD TO GND (pF)
CAP
E
RRO
R
(
fF
)
0
–20
–10
–30
–40
50
100 150 200 250 300 350 400 450
550
2.7V
3.0V
3.3V
5.0V
Figure 7. Capacitance Input Error vs. Capacitance Between SHLD and GND;
CIN(+) to GND = 8 pF, VDD = 2.7 V, 3 V, 3.3 V, and 5 V
10
–50
0
600
500
0
546
9-
0
08
CAPACITANCE SHLD TO GND (pF)
CAP
E
RRO
R
(
fF
)
0
–20
–10
–30
–40
50
100 150 200 250 300 350 400 450
550
2.7V
3.0V
3.3V
5.0V
Figure 8. Capacitance Input Error vs. Capacitance Between SHLD and GND;
CIN(+) to GND = 25 pF, VDD = 2.7 V, 3 V, 3.3 V, and 5 V
10
–50
0
600
500
0
546
9-
0
09
CAPACITANCE CIN TO SHLD (pF)
CAP
E
RRO
R
(
fF
)
0
–20
–10
–30
–40
50
100 150 200 250 300 350 400 450
550
2.7V
3.0V
3.3V
5.0V
Figure 9. Capacitance Input Error vs. Capacitance Between CIN(+) and SHLD;
CIN(+) to GND = 8 pF, VDD = 2.7 V, 3 V, 3.3 V, and 5V
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