VDD = 2.7 V to 3.6 V, or 4.75 V to 5" />
參數(shù)資料
型號: EVAL-AD7747EBZ
廠商: Analog Devices Inc
文件頁數(shù): 24/28頁
文件大小: 0K
描述: BOARD EVAL FOR AD7747
標(biāo)準(zhǔn)包裝: 1
傳感器類型: 觸摸,電容式
接口: I²C
電源電壓: 2.7 V ~ 5.25 V
嵌入式:
已供物品: 板,纜線,CD
已用 IC / 零件: AD7747
產(chǎn)品目錄頁面: 781 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: AD7747ARUZ-REEL7-ND - IC CONV CAP TO DIG 24BIT 16TSSOP
AD7747ARUZ-REEL-ND - IC CONV CAP TO DIG 24BIT 16TSSOP
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AD7747
Rev. 0 | Page 5 of 28
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; 40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SERIAL INTERFACE1, 2
SCL Frequency
0
400
kHz
SCL High Pulse Width, tHIGH
0.6
μs
SCL Low Pulse Width, tLOW
1.3
μs
SCL, SDA Rise Time, tR
0.3
μs
SCL, SDA Fall Time, tF
0.3
μs
Hold Time (Start Condition), tHD;STA
0.6
μs
After this period, the first clock is generated
Setup Time (Start Condition), tSU;STA
0.6
μs
Relevant for repeated start condition
Data Setup Time, tSU;DAT
0.1
μs
Setup Time (Stop Condition), tSU;STO
0.6
μs
Data Hold Time, tHD;DAT (Master)
0
μs
Bus-Free Time (Between Stop and Start Condition, tBUF)
1.3
μs
1 Sample tested during initial release to ensure compliance.
2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
05
46
9
-00
2
SCL
SDA
PS
tHD;STA
tLOW
tR
tHD;DAT
tHIGH
tF
tSU;DAT
S
tSU;STA
tHD;STA
tSU;STO
P
tBUF
Figure 2. Serial Interface Timing Diagram
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