參數(shù)資料
型號： EVAL-AD7765EDZ
廠商： Analog Devices Inc
文件頁數(shù)： 15/33頁
文件大小： 0K
描述： BOARD EVAL AD7765
標準包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 156k
數(shù)據(jù)接口： 串行，SPI?
輸入范圍： ±3.2768 V
在以下條件下的電源（標準）： 300mW @ 156kSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7765
已供物品： 板
AD7765
Rev. A | Page 21 of 32
AD7765 FUNCTIONALITY
SYNCHRONIZATION
The SYNC input to the AD7765 provides a synchronization
function that allows the user to begin gathering samples of the
analog front-end input from a known point in time.
The SYNC function allows multiple AD7765 devices, operated
from the same master clock that use common SYNC and RESET
signals, to be synchronized so that each ADC simultaneously
updates its output register. Note that all devices being synchro-
nized must operate in the same power mode and at the same
decimation rate.
In the case of a system with multiple AD7765s, connect
common MCLK, SYNC, and RESET signals to each AD7765.
The AD7765 SYNC pin is polled by the falling edge of MCLK.
The AD7765 device goes into SYNC when an MCLK falling
edge senses that the SYNC input signal is logic low. At this
point, the digital filter sequencer is reset to 0. The filter is held
in a reset state (in SYNC mode) until the first MCLK falling
edge senses SYNC
Where possible, ensure that all transitions of
to be logic high.
SYNC occur
synchronously with the rising edge of MCLK (that is, as far
away as possible from MCLK falling edge, or decision edge).
Otherwise, abide by the timing specified in Figure 35, which
excludes the SYNC rising edge from occurring in a 10 ns
window centered around the MCLK falling edge.
Keep SYNC logic low for a minimum of four MCLK periods.
When the MCLK falling edge senses that SYNC has returned to
logic high, the AD7765 filters begin to gather input samples
simultaneously. The
06519-
303
MCLK
SYNC
tS MIN
4 ×
tMCLK
tS HOLD
tS SETUP
FSO falling edges are also synchronized,
allowing for simultaneous output of conversion data.
Figure 35. SYNC
Following a
Timing Relative to MCLK
SYNC, the digital filter needs time to settle before
valid data can be read from the AD7765. The user knows there
is valid data on the SDO line by checking the FILTER-SETTLE
status bit (see D7 in Table 9) that is output with each conversion
result. The time from the rising edge of SYNC
Note that the FILTER-SETTLE bit is designed as a reactionary
flag to alert the user when the conversion data output is valid.
until the
FILTER-SETTLE bit asserts depends on the filter configuration
used. See the Theory of Operation section and the values listed
in Table 6 for details on calculating the time until FILTER-
SETTLE asserts.
OVERRANGE ALERTS
The AD7765 offers an overrange function in both a pin and
status bit output. The overrange alerts indicate when the voltage
applied to the AD7765 modulator input pins exceeds the limit
set in the overrange register, indicating that the voltage applied
is approaching an overrange level for the modulator. To set this
limit, the user must program the register. The default overrange
limit is set to 80% of the VREF+ voltage (see the AD7765
Registers section).
The OVERRANGE pin outputs logic high to alert the user that
the modulator has sampled an input voltage greater in magni-
tude than the overrange limit as set in the overrange register.
The OVERRANGE pin is set to logic high when the modulator
samples an input above the overrange limit. After the input
returns below the limit, the OVERRANGE pin returns to zero.
The OVERRANGE pin is updated after the first FIR filter stage.
Its output changes at the ICLK/4 frequency.
The OVR status bit is output as Bit D6 on SDO during a data
conversion and can be checked in the AD7765 status register.
This bit is less dynamic than the OVERRANGE pin output. It is
updated on each conversion result output; that is, the bit
changes at the output data rate. If the modulator has sampled a
voltage input that exceeded the overrange limit during the
process of gathering samples for a particular conversion result
output, then the OVR bit is set to logic high.
O
V
E
RRANG
E
P
IN
O
UT
P
UT
LOGIC
LEVEL
HIGH
LOW
O
V
R
BI
T
LOGIC
LEVEL
HIGH
LOW
OUTPUT FREQUENCY
OF FIR FILTER 1 = ICLK/4
OVERRANGE
LIMIT
OVERRANGE
LIMIT
ABSOLUTE INPUT
TO AD7765
[(VIN+) – (VIN–)]
OUTPUT DATA RATE (ODR)
(ICLK/DECIMATION RATE
t
06519-
016
Figure 36. OVERRANGE Pin and OVR Bit vs. Absolute Voltage
Applied to Modulator
The output points from FIR Filter 1 in Figure 36 are not drawn
to scale relative to the output data rate points. The FIR Filter 1
output is updated either 16× or 32× faster than the output data
rate, depending on the decimation rate in operation.
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