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參數(shù)資料
| 型號： | EVAL-AD7765EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/33頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD7765 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 156k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | ±3.2768 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 300mW @ 156kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7765 |
| 已供物品： | 板 |
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AD7765
Rev. A | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VOUTA+
VINA+
VOUTA–
AVDD2
VIN+
VIN–
VINA–
VREF+
REFGND
AVDD4
RBIAS
AGND1
AVDD1
AGND3
OVERRANGE
SCO
FSI
SDO
FSO
AVDD2
AGND2
MCLK
SYNC
SDI
RESET/PWRDWN
DVDD
DEC_RATE
AVDD3
AD7765
TOP VIEW
(Not to Scale)
06519-
005
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
24
AVDD1
2.5 V Power Supply for Modulator. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF capacitor.
7 and 21
AVDD2
5 V Power Supply. Pin 7 should be decoupled to AGND3 (Pin 8) with a 100 nF capacitor. Pin 21 should be
decoupled to AGND1 (Pin 23) with a 100 nF capacitor.
28
AVDD3
3.3 V to 5 V Power Supply for Differential Amplifier. This pin should be decoupled to the ground plane with a
100 nF capacitor.
25
AVDD4
3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to AGND1 (Pin 23) with a 100 nF
capacitor.
17
DVDD
2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to the ground plane with
a 100 nF capacitor.
22
RBIAS
Bias Current Setting Pin. This pin must be decoupled to the ground plane. For more details, see the Bias
Resistor Selection section.
23
AGND1
Power Supply Ground for Analog Circuitry.
20
AGND2
Power Supply Ground for Analog Circuitry.
8
AGND3
Power Supply Ground for Analog Circuitry.
26
REFGND
Reference Ground. Ground connection for the reference voltage.
27
VREF+
Reference Input.
1
VINA
Negative Input to Differential Amplifier.
2
VOUTA+
Positive Output from Differential Amplifier.
3
VINA+
Positive Input to Differential Amplifier.
4
VOUTA
Negative Output from Differential Amplifier.
5
VIN
Negative Input to the Modulator.
6
VIN+
Positive Input to the Modulator.
9
OVERRANGE
Overrange Pin. This pin outputs a logic high to indicate that the user has applied an analog input that is
approaching the limit of the analog input to the modulator.
10
SCO
Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of this clock is equal
to ICLK. See the Clocking the AD7765 section for further details.
11
FSO
Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide.
12
SDO
Serial Data Out. Data and status are output on this pin during each serial transfer. Each bit is clocked out on an
SCO rising edge and is valid on the falling edge. See the AD7765 Interface section for further details.
13
SDI
Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI event is latched.
Thirty-two bits are required for each write; the first 16-bit word contains the device and register address and
the second word contains the data. See the AD7765 Interface section for further details.
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